Save. Share. Connect.
Friday, December 2, 2016
VOLUME - NUMBER
PCB and Test
Test and Assembly
SMT and Assembly
Assembly and Production
PCB and Production
Assembly and Production
PCB and Assembly
Assembly and Packaging
PCB and Manufacturing
SMT and Production
Test and Measurement
Components and Distribution
Production and Packaging
Test and Measurement
Add Message Board
High Performance Probe Sockets
A BGA socket designed for 1GB Mobile DDR2-S4 SDRAM — 12 x 12mm, 0.5mm pitch, 168 FBGA Package.
By Ila Pal, Ironwood Electronics, Burnsville, MN
The evolution of cell phones to today's high-end smart phones with a multi-core applications processor and memory has driven the industry to embrace 3D packaging solutions. 3D packaging can be achieved by die stacking in one package, package-in-a-package stacking or package-on-package stacking. Each method has its advantages and disadvantages. Package-on-package stacking, which has been evolved into a variety of formats, enables stacking of packages from different suppliers and mixed IC technologies. It also allows for burn-in and testing before the actual stacking is performed.
In a typically stacked package, the bottom package is the processor and the top package is memory. Because of additional applications required by today's consumer demands, IC engineers have been adding more features to their 2nd generation processor, while the memory performance is increased by faster communications with the processor.
Faced with such a high level of complexity, test engineers need a socket which can test the 1st generation processor and memory. We have seen many product offerings for this one level stacked socket. In order to move from 1st generation to 2nd generation devices, a test engineer needs a 2, 3, or 4 level stacked socket. During the development phase, the test engineer needs to use a processor probe in between the processor and the main development board to connect with a logic analyzer to perform the signal capability functions. Then the test engineer uses a memory probe in between the memory and processor to verify the performance of the newer memory.
Typical four-level interconnect enabling development sequence of 3D ICs.
A typical four-level interconnect will enable the development sequence of 3D ICs. Designing a socket to accommodate these variations encounters many challenges. There are two major challenges to be addressed: force and alignment.
The most difficult of all challenge is force balancing. In a simple case, the processor has 515 solder balls and the PoP (Package on Package) memory has 168 solder balls. The memory, with its 168 balls, requires 5-lbs. of force for optimum compression that results in less than 20 milliohms of contact resistance per ball. The processor, with 515 balls, requires 15-lbs. of force for optimum compression, resulting in less than 20 milliohms of contact resistance per ball. In order to balance the force at each level, another 10-lbs. of force is needed at the memory level. This will balance the force at processor level. When 15-lbs. of force is applied to the memory with only 168 balls, the elastomer underneath memory will be over-compressed. In addition, there is the potential danger of memory device warpage due to this high force. To counterbalance, a sheet of rubber whose thickness can fill the gap between bottom side of memory device and top side of elastomer interface is used. This rubber can absorb the extra 10-lbs. of force resulting in only the recommended force on the elastomer section that has been interfaced with the memory device. Similar force balancing has to be performed at each level of interconnection if there is a force variation.
Probe Socket Configurations
The actual measurements are addressed by a recently introduced series of high-performance BGA sockets for high-speed probing of the memory chip and processor debugging during the design phase.
The customer can use this stacked socket to probe a 1GB memory device using Agilent's Flex Probe stacked inside the socket. Agilent's probe makes contact with the target PCB through the 0.5mm thick high density elastomer contact. The memory chip sits on top of the probe and makes contact with it using high-speed elastomer contacts. The Agilent probe brings the signals out to oscilloscope/logic analyzer for high-speed probing.
If an available configuration is not suitable, the first step in procuring a custom probe socket is to communicate the device specifications to Ironwood Electronics. An application engineer will be assigned to meet this request, and will work with the customer's design engineer to produce a custom probe socket drawing that shows footprint and stack-up information. A proposal will be sent to the customer after acceptance of the custom probe socket drawing.
The company provides various options such as first article, delivery schedule and quantity price breakdowns. At the start of the project, an application and design engineering team will work on the new project and will keep the customer updated on schedules and project milestones.
Similar to force balancing, alignment level challenges have been addressed at each interconnection level. Let us consider a simple case where a test engineer needs to test the processor only. It is a simple one-level interconnection.
Table 1: Off-the-shelf Probe sockets compatible with Agilent's memory probe.
The top side of the elastomer interfaces with device's balls and brings the electrical signal down to the test board. The elastomer consists of gold-plated brass wires embedded in silicone rubber. In order to have the lowest resistance electrical path, more than 50 percent of area — pad/ball dimension — must make contact with the top and bottom sides. To ensure proper alignment, all of the components are precisely positioned with one alignment pin.
Worst Case Scenario
In a worst case scenario, the PCB alignment hole position is +0.025mm; the Ball guide Alignment Hole position +0.025mm; and the PCB Pad location/Size is +0.05mm; the result is a total of 0.1mm off from nominal location alignment.
With 0.24mm minimum pad diameter for 0.4mm pitch BGA, the elastomer contacts more than 58 percent of the pad with 0.1mm off from nominal location. This means that the pin alignment hole and ball alignment hole have to be manufactured with very tight tolerance ±0.025mm. This XY variation occurs on each level of the stack up.
All the levels should ensure greater than 50 percent contact coverage area for the best electrical connection. Similar calculations have to be made for Z variations and manufacturing tolerances have to be updated such that >50 percent of pad is covered by elastomer. Alternatively, if spring pins are used instead of embedded wire elastomer for interconnect options, the alignment challenge increases two fold.
First, we have to add spring pin diameter tolerance. Then, we have to add the tolerance for the hole that positions the spring pin. In order to ensure the proper electrical connection, manufacturing tolerances have to be very tightly controlled for these two additional factors — causing yield issues and high cost. Thus selecting the appropriate interconnect medium plays a major role in development cost.
Contact: Ironwood Electronics, Inc., 11351 Rupp Dr., Suite 400, Burnsville, MN 55337
800-404-0204 or 952-229-8200 fax: 651-452-8400 E-mail: firstname.lastname@example.org Web:
© 2015 USTECH. All Rights Reserved. |
Contact Us: 610-783-6100 | email@example.com
powered by GIM