Thursday, September 29, 2016
VOLUME -26 NUMBER 8
Publication Date: 08/1/2011
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Archive >  August 2011 Issue >  Special Features: Test and Measurement > 

Boundary-Scan: The Technology Has Grown Up
High-end JT 37 x 7/RMI boundary-scan controller from JTAG Technologies.

Boundary-scan PCB testing has come of age largely because of easy-to-use and highly automated tools for developing boundary-scan tests. In addition, a newer range of low-cost or even no-cost test utilities have made this technology even more accessible. As a bonus, today's JTAG is also increasingly used for in-system programming of flash memories and PLDs, embedded processor flash and as a debugging interface for MCPs, DSPs and SoCs.

Today, boundary-scan is a standard feature of most 16-bit and higher MCPs and MCUs — Freescale's iMX, QUICC, Coldfire and Dragonball series; Intel's Pentiums; Marvell's PXA, Microchip PIC, Renesass SuperH; and TI's TMS 320 series DSPs. Boundary scan is also included in up-to-date editions of some 8-bit systems.

Now, new second-generation JTAG application development tools are making it easy to create tests and program devices.

IEEE Std. 1149.1
An IEEE 1149.1 compliant device contains additional logic and a JTAG interface to enable access to this logic. The device's digital pins each have a boundary-scan cell or cells, which are transparent during normal operation. These cells together form the boundary-scan register. In normal operational mode, the core controls the pins of the chip. In test mode, the boundary-scan register takes over the control of these pins, and the individual bits of the boundary-scan register are used to drive and sense the device pins independent of the core of the chip. In addition to this register, the device will also have the bypass- and instruction-register, and any number of additional optional data registers such as an ID-register. The boundary-scan register logic for digital device pins is defined in IEEE Std. 1149.1 (dot 1). IEEE Std. 1149.4 (dot 4) — which is in addition to dot 1 and was released in 1999 — describes the boundary-scan logic for analog pins in mixed-signal devices. High-speed digital pins in advanced digital networks (capacitor-coupled connections) require some additional logic (pulse generator at the driver and an edge detector at the sensor) as defined in another addition to dot 1 released in 2003, IEEE Std. 1149.6 (dot 6).

JTAG Registers and Instructions
For test purposes, the boundary-scan register and the instruction set have proven to be more than sufficient over the years, providing an effective and low-cost means to test often inaccessible circuit tracks and components. Boundary-scan registers facilitate structural testing of boards providing known fault coverage and immediate diagnosis down to the pin level. Tests like: continuity checks, structural interconnect test, (functional) cluster test and memory interconnect test are easily possible. To simplify the testing of their interconnects, future memory devices may contain special test logic defined in a new standard released earlier this year: IEEE Std. 1581 for Static Component Interconnection Test Protocol and Architecture.

Thoughtful use of test access provided by boundary-scan has also enabled users to create flash in-system programming applications for NOR and NAND types and also serial PROMs such as I2C and SPI with relative ease.

JTAG in cPLDs
Today's programmable logic devices — such as cPLDs and FPGAs — are equipped with JTAG interfaces that support JTAG programming. Programmable logic vendors such as Altera, Cypress, Lattice and Xilinx were all early adopters of JTAG technology, but not always in order to use its test features. The attraction of boundary-scan for these silicon vendors was a programmer interface that allowed register access to program the macrocell and gate fuse maps. Early in the development process, each vendor devised a methodology and instruction set to implement this programmability. However, by the late 1990s, a common PLD programming standard working group was established, which utilized input from test system developers — including JTAG Technologies as well numerous cPLD vendors — to create a new standard. This became IEEE Std. 1532 for In-System Configuration of Programmable Devices, and was approved in 2000. This standard specifies a minimum set of data registers and programming instructions that define a standard methodology for configuring programmable devices through the JTAG port. It also specifies an extension to BSDL facilitating standardized automation tools for device programming.

JTAG in Micros
Just as PLD vendors used and built on the capabilities of boundary-scan, so too did microprocessor vendors who also fitted basic boundary-scan functionality, allowing structural board tests prior to board and system level functional tests. However, while the PLD vendors focussed on adding functions for ISP, microprocessor vendors added emulator and debugging functions providing the ability to load, run, halt, and step the CPU, thus enabling the software engineer to debug CPU code via the JTAG interface. The debug logic can also be used for emulative testing of the processor kernel of a board.
A typical device with JTAG logic. The JTAG interface is called the Test Access Port, or TAP. Data comes into the device on the Test Data In (TDI) pin and exists on the Test Data Out (TDO) pin.


At first, JTAG could only be found on larger, top-end 32-bit (now 64-bit) MCPs and a few 16-bit MCUs. However, many silicon companies are now implementing boundary-scan across the board. Si labs, for example has an 8051 derivative MCU device — the C8051-F120, with full boundary-scan and on-board JTAG debugging plus embedded flash — which can also be programmed by register access from the JTAG port. This, along with analog inputs and DIO ports, all comes in a 64-pin package.

For devices like microprocessors it may be desirable to control the power consumption of the debug logic, or to quickly access a specific IP block on a System-on-Chip device to improve the software debugging performance. This additional functionality is defined in IEEE Std. 1149.7 and can be accessed through the JTAG port, or alternatively through a reduced pin-count TAP defined in Dot 7. The official name for Dot 7 is IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture. The standard was released in 2009 and complements the Dot 1 standard with which it is backwards compatible.

JTAG in SoCs
Besides microprocessor debug logic, other types of instrumentation are built into devices for (chip internal) test and measurement purposes. Another additional associated standard, IEEE P1687 (IJTAG), "Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device", is now under development. It will describe the methodology for access to the embedded instruments through the JTAG port, and will provide a standardized description format how to operate the instruments to facilitate their use and re-use at board and system level in a standardized way. Like others also this standard is an extension to the original Dot 1 standard.

With the continuously increasing availability of IEEE 1149.1 compliant devices in evidence, more and more engineers are harnessing the power of JTAG and formalizing test techniques for the first time. There is now an array of supporting products to choose from, ranging from free license, downloadable utilities — such as JTAG Live Buzz for interactive pin-to-pin continuity testing — to full-blown automated test and ISP application development suites such as JTAG ProVision.

Because boundary-scan controls the I/O pins of JTAG-compliant devices on a powered board, it is important to consider what effect running the boundary-scan tests will have on non-boundary-scan parts.
Routing of boundary-scan on a printed circuit board highlighting boundary-scan applications. Also various IEEE standards with their first year of release are indicated for reference purposes.


In the case of low-cost and free tools, it is the engineer's responsibility to determine the safe conditions under which the boundary-scan driver can be activated, to avoid causing interference with non-boundary-scan device drivers. This is often done by setting pin states that control reset pins or chip enables in a constraints section of the tool.

More advanced tools such as ProVision can automate boundary-scan applications generation, as models are provided for non-boundary-scan compliant parts. With these models in place, creating safe test conditions is fully automated and this is a major plus for engineers in that it saves time and takes the risks out of the tests. The device models for non-boundary-scan compliant parts cannot only be used to disable active parts but may also include the test patterns needed for functional checking of the parts (cluster testing). In addition to boundary-scan software development tools, the associated hardware has come a long way since the standard was first introduced. Controllers with multiple TAPs enable engineers to design circuit boards with more than one boundary-scan chain, thus providing the option for a dedicated chain for faster flash programming. Additional tester TAPs also make through connector testing simpler using an auxiliary digital I/O scan hardware module, accessing the board edge and/or test points. Such modules contain JTAG-compliant parts that synchronize with those on the board, and their use can lead to near 100 percent test coverage.

Contact: JTAG Technologies, 111 N. West Street, Easton, MD 21601 877-367-5824 fax: 410-770-4774 Web:
http://www.jtag.com

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