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Publication Date: 08/1/2011
ARCHIVE >  August 2011 Issue >  Special Features: Test and Measurement > 

Boundary Scan: Test More, Pay Less
Example of typical BGA component.

Today's test engineer is faced with a multitude of test technologies. The most common and best known test technologies are divided into two groups: optical and electrical.

Optical Test Methods include Manual inspection (MI), Automated Optical Inspection (AOI), and Automated X-Ray Inspection (AXI). Electrical Test Methods commonly used are Multi-functional Test (MFT), In-Circuit Test (ICT), Flying Probe Test (FPT), and Boundary Scan (BScan).

An optical technology is logically able to detect visible faults, e.g. missing components, wrong placement or wrongly polarized components. It also offers the opportunity to make a qualitative evaluation of solder joints. An optical test, however cannot provide test information on a product's electrical performance.

The performance of a circuit component can be verified only by electrical test. Such a test will determine if a resistor is the correct value or if an IC's output driver works. Unlike the antiquated MFT, free access to all parts of the assembly or the individual component pins is not necessary with today's test technology. Further, MFT could not make qualitative evaluations about solder joints and was not able to detect a mechanical component defect.

Each test technology has its advantages and disadvantages. Nonetheless, if it's about speed, test coverage or mechanical access, no single test method can be seen as a universal remedy. That's why it becomes necessary to combine the best areas of the different test methodologies.

Combining BScan and MFT
When using the Aeroflex 5800 Series Multi-functional test system, the integration of JTAG/Boundary Scan became a critical factor in guaranteeing high test coverage for assemblies that yielded only a few contact points. The high cost in time and money to develop digital functional test modules for complex components sends test engineers into the arms of boundary scan. This technology is extraordinarily convenient for testing ID codes as well as correct mounting and soldering of components — instead of testing the component function.
A Boundary Scan IC's architecture reveals that its cells are located between component pins and its core logic.

Both JTAG/Boundary Scan and In-Circuit Test are purely electric test technologies with certain similarities. The conductive paths (nets) are stimulated at one point and measured at another point. Information based on this measurement can infer that potential faults exist on a PCB. The main difference between Boundary Scan and ICT is their access to the nets. The ICT needs to contact the tracks mechanically using predefined test points on a board. Boundary Scan, on the other hand, is a purely electronic method that utilizes additional logic which is integrated into many complex components.

Four-Wire Test Bus
The necessary information transfer between test system and Boundary Scan component is executed via a four-wire test bus, which must be included in the PCB design. Once a circuit is designed for Boundary Scan, a test system will need only a connection for this test bus. The Boundary Scan cells are located between component pins and its core logic. The inner component logic does not play a role in testing circuits on an assembly, regardless of whether it is a processor or PLD. Layout display is simplified as test points, is required, are few in number.

In order to simplify the integration of other vendors' test and measurement instrumentation into the 5800 Series Multi-functional test system, market standard open software and hardware platforms were selected. The Aeroflex chassis utilizes an MXI-4 card for communication with the PC, a 3U PXI backplane to integrate any PXI modules, combined with a special Aeroflex backplane for internal signals for fast In-Circuit test as well as analog and digital functional test.
Test points on a PCB.

The interactive open software environment AIDE (Aeroflex Integrated Development Environment) allows for the integration of .NET compliant third party software — Teststand, Labview, C#,or VB.NET.

  • Each .NET programming environment has access and can control the hardware of the 5800 multi-functional test system.
  • AIDE can use the code generated in a .NET programming environment during development or sample test, for PCB testing.
  • Systems with DLL, .NET or Active X drivers can be controlled with AIDE.
  • Programs created with AIDE can be executed in each .NET capable software environment.
  • Older non .NET compliant drivers can also be integrated by means of tools included in the software.

Digital Functional Test
The digital functional test subsystem of the 5800 supports the JTAG/Boundary Scan standard (IEEE 1149.4) and can be combined with a Boundary Scan system from GOEPEL electronic. The integrated Boundary Scan hardware consists of a PXI or PCI controller, a TAP Interface Card (TIC) and various I/O modules. By utilizing digital and analog I/O modules, the multi-functional test system's test coverage is significantly increased. The controller's architecture supports data rates up to 80MHz and up to eight independent TAPs (Test Access Ports).

The Boundary Scan test programs can be controlled by the AIDE development environment. This is helpful, as programs generated for new products or prototype tests, can be reused in production tests. During the Boundary Scan test, the vectors can be switched directly to the UUT from DTP cards and additionally stimulate the test object, can check the behavior of peripheral components if applicable. The transparent handling of the fault report by the AIDE environment provides for complete integration into the test program. The predefined test opportunities of Goepel's SYSTEM CASCON Boundary Scan software can be extended by integration into the 5800 digital test system. All 5800 Digital Test Point (DTP) cards contain Boundary Scan cells, and thus, can be utilized like a Boundary Scan component with input and output pins. Hence, non-Boundary Scan circuits on the board, which are contacted by Aeroflex DTP test pins, can be used for a Boundary Scan test.

The DTP card?s test pins are organized into four groups with 16 test pins each. The configuration for each group is described in a BSDL file. These BSDL files are an integral part of the 5800's system software. All other TDI and TDO are connected internally.

Programs and tests developed by the SYSTEM CASCON tool suite can be directly executed by the SYSTEM CASCON Boundary Scan library in the AIDE program. All methods and variables are defined in the library. Using the modules in the library, users can execute specific tests according to their requirements.

This synthesis of Multi-functional Test and Boundary Scan benefits not only test and repair engineers, but also PCB designers. Throughput, test and production costs can be expected to be reduced earlier in the production process, and still provide extensive fault detection. Another advantage of this combination of test technologies is the constant improvement of the production process — for both prototypes and large volume production.

Contact: Goepel electronics LLC, 9600 Great Hills Trail, Suite 150W, Austin, TX 78759 888-446-3735 or 512-782-2500 E-mail: Web: or

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