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Increased Probe Density with Guided Pin Fixturing
Schematic of the guided pin fixturing concept.

Although other test and inspection technologies such as automated optical inspection have tried to supplant it, in-circuit test (ICT), which has been around since the 1970s, still delivers the highest test coverage with the least diagnostic ambiguity at the least cost for circuit board structural test. There's just one big problem that has been there all the time: the custom-built bed of nails (BoN) fixture that connects the board under test to the tester itself.

As boards have become larger and denser, the bed-of-nails problem has only grown more complex — and more expensive. Smaller and smaller test probes, now down to 0.395-in. in diameter, have reached their practical lower limit. Fixture wiring is a time-consuming, error-prone process, particularly for large boards, many of which routinely exceed 2,500 circuit nodes.

Nowhere is the problem more severe than at the new product introduction (NPI) phase. Building and releasing a BoN fixture to production on time and on budget can be a challenging task even for relatively straightforward boards of just one or two thousand circuit nodes. But for large boards — those whose circuit node count can exceed 7,000, and physical sizes exceeding 18 X 24-in. (457 x 609mm) — the test application development process morphs from the merely challenging to the totally risky.

A single bed-of-nails fixture for a large board to be used on a traditional "big iron" ICT systems such as those from Agilent or Teradyne may cost upwards of $60,000 and require a fixture design, build and verification time of four to six weeks. The NPI process only amplifies this problem. Boards may involve up to five distinct board design and layout changes such that the next iteration of the prototype or pilot board requires a completely new BoN fixture. This reality leads to profound cost consequences that in some cases can be as large as $150,000. Even in volume production, today's large, very dense boards require custom-designed, handcrafted BoN fixtures costing upward of $30,000 each, when built for use on traditional "big iron" ICT.

Flying Probers
Flying probers have been a partially successful attempt to retain the diagnostic advantages of ICT while eliminating the bed-of-nails fixture. In fact, flying probers now account for almost one quarter of total ICT consumption, as measured in unit sales per year, and are found in numerous NPI lines, and other high-mix/low-volume board assembly environments for both OEMs and contract manufacturers. But a frequently heard complaint is, "The flying probers we use for NPI and high mix requirements are too slow and their coverage is poor." Just in terms of test time, one OEM found that a large board of approximately 7,000 nodes, which took five-minutes to test on a traditional ICT, required 3.5 hours to be tested on the flying prober — and this with poorer fault coverage. This means that for a typical NPI production run of 20 boards, the total test time would have exceeded 70 hours, assuming perfect boards and no retest requirements.

Thus the challenges are:

  • Test engineers would prefer to use in-circuit test over flying probers because of ICT's superior throughput and fault coverage.
  • The traditional hand-wired BoN fixtures needed for ICT are too expensive and have unacceptably long delivery times, particularly for large node count (>2500) boards.

What's needed is a new BoN fixturing system and companion ICT system that overcome the traditional cost and delivery shortcomings of traditional ICT fixtures. Both the fixture and the ICT system on which the fixture sits need to be scalable to large boards, preferably with no upper node count limit and stay within acceptable cost limits. Finally, given the density of today's boards, improved contact reliability for very small target areas — down to 0.20-in. (5.08mm) — is required, as well.

This was the design challenge that confronted the fixture design engineers at Everett Charles Technologies (ECT) and the test system engineers at CheckSum.
The guided pin fixturing system achieves very high probe densities while simultaneously eliminating traditional fixture wiring.

Their collaborative design solution started with ECT's long experience with bare board testing, using a proven probing technology that eliminates point-to-point wiring, while reducing cost and improving contact reliability. This "guided pin" fixturing design approach uses multiple drilled and stacked plates, which mechanically guide each probe, accurately "tilting" it to its specified target. The probes can be as close as 0.5mm (0.20-in.) on center. The bottom of each probe contacts a spring-loaded pin, which is in the fixture interface, 0.100-in. (2.54mm) on center. Depending on fixture size required, the interface can have up to 50,000 pins, although there is no theoretical upper limit to the number of pins.

Eliminating the wiring used in conventional BoN fixtures delivers two significant benefits that make it the preferred solution for boards of all sizes in the NPI, high-mix/low-volume and high volume production environments:

  • Guided pin fixtures cost half as much per point as traditional wired fixtures.
  • Guided pin fixtures have turnaround times half that of traditional wired fixtures.

Pin/probe assignment software matches each guided pin that contacts the underside of the board with the closest and most appropriate fixture interface pin, thereby eliminating conventional fixture wiring. The software also takes into account the presence of other in-fixture structures such as TestJet® bottom sensors. Multiple resources may be connected to a single point, allowing activities such as on-board part programming. The fixturing system can also be employed with dual stage fixture strategies.

The Right Test System
However, a fixturing solution is worthless without the right test system underneath it. While the guided pin fixture can be adapted to the multiplexed channel architecture of traditional "big iron" ICT, many of the technical benefits of the fixturing system are lost. Each guided pin must be routed to a particular channel by the tester's pin assignment software. This means that the fixture must be wired in conventionally, eliminating almost all the cost and fast turnaround time benefits of the guided pin fixturing system. Of even greater concern to OEMs and contract manufacturers building larger boards is that the maximum pin count limitations of traditional ICT will not accommodate large node count boards of greater than a few thousand circuit nodes. Moreover, with their high per-channel cost, traditional ICT systems with high channel counts become enormously expensive.

To optimize the benefits of the guided pin fixture system, the ICT system must have:

  • Non-multiplexed channel architecture.
  • Much higher upper limit on channel count than traditional ICT; no upper limit is preferable.
  • Low per-channel cost so that the cost of large channel count systems remains realistic.

The key insight to the ICT system design was to recognize that today's boards — regardless of their size — are substantially different that those produced in the 1990s, when the architectures and capabilities of traditional ICT systems were designed. As component packaging and board assembly technologies have advanced over the past decade, the fault spectrum — the distribution of defect categories found on typical boards — has shifted radically. The biggest shift of all is that today's digital devices are vastly faster, more complex and more reliable than before. Moreover, today's boards incorporate far more built-in self-test (BIST), usually in the form of boundary-scan.

Digital Channels
The resulting test methodology: the high capability but very expensive digital channels found on traditional ICT can be eliminated from today's ICT, vastly reducing per-channel cost. In turn, low cost allows straightforward non-multiplexed channel architectures, and effectively eliminates the upper limit on channel count. This newest ICT architecture is an excellent match for today's boards, including those with very large node counts, especially those employing boundary-scan and other forms of BIST. Thus today's ICT system has:

  • Non-multiplexed architecture required to preserve the key cost and turnaround time benefits of guided pin fixturing system.
  • Full test system capabilities that meet requirements of boards with BIST, including boundary-scan.
  • Unlimited upper pin count to handle large boards.
  • Low system and per-channel cost consistent with the low cost philosophy of the guided pin fixtures — half the cost delivered and twice as fast as conventional BoN fixtures.

This combination of guided pin fixturing system with an up-to-date non-multiplexed ICT architecture restores ICT to its rightful place as the preferred structural test strategy for electronic manufacturers. It does this by delivering higher fault coverage on complex boards at lower cost and in less time than traditional ICT or flying probers.

Contact: CheckSum LLC, P.O. Box 3279, Arlington, WA 98223 360-435-5510 E-mail: Web: or Everett Charles Technologies, One Fairchild Square, Clifton Park, NY 12065 518-877-7042 E-mail: Web:

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