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Publication Date: 07/1/2011
Archive >  July 2011 Issue >  Special Features: SMT and Production > 

Upping Performance with Through Silicon Vias
Computer model of a tapered Mechanically Flexible Interconnect (MFI), a tiny, coiled, tapered spring that can be formed at the wafer level.

Through Silicon Vias (TSVs) have been at the center of discussions of 3D integration in recent years, and are now beginning to appear in production. The concept, though, is not new. William Shockley, one of the inventors of the transistor, described and patented TSVs (without calling them that) in U.S. Patent #3,044,909, filed in 1958 and issued in 1962. But it took half a century for the production technology to reach the level of expertise that would actually permit making TSVs.

The idea of a TSV is simple enough. Holes are etched through silicon die, generally in wafer form, and then plated with copper. The copper makes it possible to connect one device with another device placed on top of it, and eliminates the need to use wires. Instead of placing two die — memory and a processor, for example — in different locations on a board and interconnecting them with wires and traces, they are stacked on top of each other and connected by TSVs. It is currently possible to stack up to thousands of TSVs per square centimeter. Solder bumps are typically used to join the two TSVs, although a very different technology, referred to as MFIs, is on the horizon.

Communication between the two die is much faster because the distances are so much shorter. A second advantage: regions of circuitry that frequently talk to each other can be placed at opposite ends of the same TSV. And stacking two or more thinned die in this way means that applications that demand higher speed, greater performance and smaller size can benefit greatly from the much higher interconnect density that TSVs provide.
Diagram showing TSVs and MFIs connecting a MEMS chip to a CMOS processor — MEMS sensor IC with three different possible types of sensor arrays, and the use of MFIs and TSVs to make the high-density, stress-tolerant connections between the sensor IC and the CMOS processor below it.

One of the leaders in TSV research, and particularly in developing techniques for fabricating TSVs, is the GigaScale Integration program at Georgia Tech. Dr. Muhannad Bakir, principal investigator in the program, points out that a few products using TSVs are already in production, and that several companies have announced that they will shortly be releasing products that use TSVs.

A Few Microns Across
The diameters of TSVs vary from a few microns to many tens of microns, depending on where they are used. By far the smallest are the die-to-die TSVs made in fabs. It might be tempting for back-end manufacturers to think about doing their own TSVs, but Dr. Bakir thinks that this technology will remain firmly in the hands of the IBMs and Intels of the world. The technology is difficult, and it would be very difficult for companies from other disciplines to try to catch up.

The TSVs used in silicon interposers, however, are considerably larger and easier to form, and Dr. Bakir points out that many silicon interposer applications are currently in development. A silicon interposer consists of one or more metal interconnect layers on a silicon substrate, with TSVs connecting one side of the interconnects to the bond pads on the other side. They can be used as a simpler way to connect multiple ICs using fine pitch horizontal wiring, or to connect a high-density IC to a lower-density organic substrate. The latter application — bridging the dimensional in feature sizes in an advanced IC and the printed wiring board — looks particularly attractive.

Xilinx used the silicon interposer approach late in 2010 when they needed to establish interconnects between a large Field Programmable Gate Array (FPGA) and its organic substrate. They used a silicon interposer and, instead of using the large, hard to manufacture and expensive FPGA, they placed on the silicon interposer four smaller, less costly FPGAs having presumably higher yields. This approach very likely had a favorable impact on reliability and costs. In Dr. Bakir's view, multiple ICs directly stacked with TSVs in fab processes, along with silicon interposers, will be areas of significant growth in the use of TSVs in the near future.

Another area of significant TSV adaptation will be MEMS (and sensor) devices. This area of growth varies from the others because of its diversity: the large and growing number of functions carried out by MEMS devices requires, at the moment, that each pair of ICs — the sensor IC and the processor — be developed individually. This is not a problem as long as they are mounted separately on a board and connected by wires and traces, but the natural evolution of MEMS devices is toward higher density, higher performance, and smaller size, a situation that demands high density and low parasitic interconnects.

Flip Chips for MEMS
Flip chips might be a better design for MEMS, since, unlike wire arrays, flip chips can be batch fabricated and have superior electrical performance. But flip chips do not lead to smaller size because they require routing and distribution through the PCB. Flip chips have another drawback: they typically require underfill, which can interfere with performance. They also can be subject to thermomechanical stress, which is sometimes great enough to crack the die. Even without physical damage, thermomechanical stress is hard on MEMS devices. In one test, the performance of a MEMS devices changed by up to 37 percent when thermomechanical stress was applied. "You don't want the device characteristics to change before and after packaging," Dr. Bakir says.

To solve these problems, Dr. Bakir's group has invented, and applied for a patent on, the Mechanically Flexible Interconnect (MFI) — basically a tiny, coiled, tapered spring that can be formed at the wafer level. The spring is tapered along its length because modeling showed that this design would more equally distribute stresses. The group is currently fabricating MFIs as small as 50 x 100 microns.
Scanning electron microscope (SEM) image of a group of MFIs after reflow.

In an example of how this works, a MEMS sensor IC can have three different possible types of sensor arrays, and the use of MFIs and TSVs make possible the high-density, stress-tolerant connections between the sensor IC and the CMOS processor below it. Together, the TSVs and MFIs carry the raw signals from the sensors to the CMOS for signal conditioning, amplification, processing, actuation and other purposes.

Relieving Stresses
MFIs are able to relieve thermomechanical stresses very effectively because the curved beam is able to be deformed in the x, y and z dimensions and spring back to its original form when stress is removed. Currently the stand-off height between the two chips is 20 microns, but MFIs for other heights are in development.

MFIs are fabricated by a multi-step process that can be performed at the wafer level, or after the end of semiconductor back-end-of-the-line (BEOL) processes. The latter option permits MFIs to be fabricated on a CMOS chip.

One potential problem in using MFIs had been that the solder, which must be placed at the high point at the end of the beam, may flow away from the intended contact point during reflow. Dr. Bakir's team solved this problem by placing a polymer ring at the tip of the beam. The polymer ring permits under-bump metallization with metals such a nickel. It also holds the solder in place during reflow. MFIs are not limited to connecting a MEMS chip to a CMOS chip. Where thermomechanical stress is a concern, they can be used to connect the CMOS chip to the substrate. They can also be used to fabricate a partly disposable MEMS package, where the MEMS chip, no longer useful because of its exposure to a substance being measured, can be removed and replaced by a new MEMS chip, thereby saving the presumably more expensive CMOS IC. This is especially important when dealing with such devices as biosensors. It is also possible to use MFIs for temporary connection to bare die for high-speed testing before mounting of the IC.

Will the combination of higher speeds, better electrical performance, and better handling of thermomechanical stresses mean that TSVs and MFIs will pose a threat to conventional wire-bonding for all products? Dr. Bakir thinks this is unlikely. Many products, he points out, perform very well using conventional wire-bonding. It is when the need for high interconnect density and heterogeneous integration pushes designers into the realm of 3-D integration that TSVs and MFIs become necessary.

Contact: Research News & Publications Office, Georgia Institute of Technology, 75 Fifth Street, NW, Suite 314, Atlanta, GA 30308 404-894-6986 E-mail: Web:

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