Save. Share. Connect.
Monday, August 21, 2017
VOLUME -26 NUMBER 7
Publication Date: 07/1/2011
Front Page News
People in the News
Electronic Mfg. Services
Electronic Mfg. Products
Special Features: SMT and Production
Product Preview: Semicon West
July 2011 Issue
Product Preview: Semicon West
Add Message Board
SPEA: Mixed Signal Test Platform
Comptest MX test platform.
Volpiano, Italy — SPEA is showing its innovative semiconductor test solutions. Its Comptest MX test platform addresses the test requirements of all mixed signal devices, including power and discretes, MEMS and sensors, power management ICs, automotive devices, lighting ICs and LED drivers, audio and video ICs, identification ICs and smart card modules.
The Comptest MX has been expressly designed to drive down the cost of test of such devices up to 50 percent, through a high-efficiency architecture that provides true per-pin architecture that achieves 99 percent parallel test efficiency in multi-die testing, with no overhead Test Time as test sites increase.
The timing for the instrument programming is generated in parallel by multiple, high-frequency CPUs, that are designed by SPEA, and it is independent from the PC performance. 64-line Synchrobus and 16-line high-speed Synchrobus provide a hardware synchronization between all the instruments, for a substantial test time saving. There are 88 slots for analog and mixed-signal instrumentation, and 1408 analog/digital channels, to give high multi-site test capabilities. Fast test program development and pattern-based test programming save the 30 percent on test time, compared to software-based linear programming.
Real parallel test is performed with programmable logic units for each pin, timing measurement units per pin, multiple channel digitizers with DSP instrumentation for fast data computation, arbitrary signal generator units for the multiple signal generation and possibility to install low-value measurement instruments with resolution as low as 3 femtoAmps. The system is especially useful in testing power analog, smart card modules and MEMS devices.
The system's power configurations offer special performance in the production test of power devices with up to 16 multi-die testing; up to 1000 Amperes, ±2500V; AC/DC test capabilities, for wafer and final test, on a single tester; dedicated CPU on HV/HI instruments and local set-up memory, for easier management of parallel function and shorter test time; automatic spike detection to avoid damage on the DUT; embedded alarms on the instruments; current generators are internally parallelable, while voltage generators are internally stackable — meaning no need for hardware on the loadboard. The company is also offering integrated test cells for MEMS devices, which integrate all the elements for handling, contacting and complete testing, including physical stimulus for functional test and tri-temp thermal conditioning.
A special feature of these test cells is that all the components are designed and manufactured directly by SPEA for integrated operation; the test cell works as a single instrument able to perform all the operations for the test and handling of MEMS devices.
The main advantages of this formulation result in: reduced costs; short application development; ease of use and maintenance; scalability and easy modification/extension of the equipment to answer new requirements; high-throughput pick-and-place test handler (18,000 UPH), specifically designed to perform gentle, fully automated handling of MEMS devices; components are picked up from trays, bowl feeder, transferred to a test area set up for the product under test and, at the end of the test, they can be placed on trays or reel.
Contact: SPEA America, 2609 SSW Loop 323, Tyler, TX 75701
903-595-4433 fax: 903-595-5003 E-mail: email@example.com Web:
at Semicon West Booth #6285.
© 2015 USTECH. All Rights Reserved. |
Contact Us: 610-783-6100 | firstname.lastname@example.org
powered by GIM