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Versatile Boundary Scan Also Programs and Debugs
JTAG/boundary scan implementation at IC level (IEEE 1149.1).
By Peter van den Eijnden, President, JTAG Technologies, Eindhoven, Netherlands
The JTAG standard IEEE 1149.1 — developed by the Joint Test Action Group — was originally developed to facilitate structural testing of assembled PCBs, as well as testing boards where it is impossible to make contact with component pins with external probes. This type of testing becomes particularly important on crowded boards filled with SMD devices and BGAs.
Structural testing looks at the physical properties of the PC board: the correct parts and the correct connections. The main advantage of this test method over functional testing is the direct diagnosis of failures. A faulty solder connection (open pin or short between different conductors) will show up in this type of test, the fault can be directly detected, and diagnosed at the pin-level. In addition, the testability of a design can be calculated directly based on the schematics. The design engineer can use the results of a testability analysis to further improve the testability of his design.
The test engineer makes a fault coverage calculation which determines if the PCB's fault coverage is less than the calculated testability of the design. If it is, then additional tests can be developed to obtain the maximum possible coverage.
The IEEE Standard
The IEEE Std. 1149.1 defines two main elements — the interface, called Test Access Port or TAP; and register logic for test purposes. The Standard also defines the register logic that is needed for testing digital pins. Two later standards define the additional logic that is needed for analog pins (IEEE 1149.4) and high-speed AC-coupled pins (IEEE 1149.6)
By using the JTAG (TAP) interface, the test engineer has serial access to the special test logic that is built into the chip. The test logic is independent of the functionality (core) of the chip and is separated from it.
An essential element of the test logic is the boundary-scan register. The test chip can operate in two modes; in functional mode, the core controls the pins of the chip. In boundary-scan test mode, the I/O pins of the chip are directly controlled by the test logic (boundary-scan register) independent of the functionality of the chip. The interface comprises four signals: TDI (Test Data In), TDO (Test Data Out), TCK (Test Clock) and TMS (Test Mode Select). A fifth interface signal, TRST (active-low Test ReSeT) is optional. On a board with boundary-scan devices, the serial test signals TDI and TDO are connected to create a chain or string, with one string TDI and one TDO. If needed, multiple strings can be created. Serial access is provided to the various test registers of the chips by using the TDI and TDO of the string.
In addition to its test definitions, IEEE Std. 1149.1 also is used for other important applications such as programming flash memories and programmable logic, as well as hardware and software debugging during prototyping. The boundary-scan technology thus not only is valuable in manufacturing, but can also be used extremely well during the debugging of the design in the prototype stage.
To test a board, the boundary-scan registers provide serial access to all pins of the chips. Using the output pin values of 1 or 0 applied to the connections and at the input pins, the values on the connections can be read back. If there is a mismatch between the values being driven and the values coming back, one or more faults are present. By applying the right combinations of 1s and 0s as test patterns, the presence of a fault and its cause (open pin or short between connections) can be discovered. It is also possible to test devices that do not contain boundary-scan logic. This is done by controlling the device inputs from boundary-scan devices and observing the outputs with boundary-scan devices. Performing such tests is called boundary-scan cluster testing, such as in testing random logic, performing memory interconnect tests where solder connections of the memory devices on the board are tested.
JTAG/Boundary-scan testing and device programming requires physical access to the UUT through the Test Access Port.
In addition to testing, the serial interface can also be used for programming flash memories, even if these memory devices themselves do not have boundary-scan. The flash memories can be treated as cluster devices. By using the surrounding boundary-scan components that provide access to the address, data, and control signals, it is possible to write and read back programming data values for flash memory.
Since the standard defines a general register structure, the test logic in a chip may contain all kinds of other registers in addition to the one for boundary-scan. These registers facilitate other applications that use the high-speed serial TAP interface. One such application is in-system programming of today's programmable logic devices (PLDs), also referred to as JTAG programming.
Boundary-scan can also be used to help debugging the hardware during the prototype stage. One of the measurements an engineer often does is the so-called "buzz" or "ring" measurement. Traditionally this measurement is done using a multi meter to check the connectivity of a particular connection — "ring-out a connection". With tiny SMD devices on the board, being able to connect the multimeter probes to the device pins has become nearly impossible. By using the boundary-scan registers in the chips the continuity measurement is still possible. Continuity measurements are also used extensively in the repair environment to check the connectivity of two pins.
A totally different application is software debugging. In this case, the internal debug logic of a microprocessor is controlled by the TAP interface. By applying different commands to the debug logic, microprocessor activity can be monitored, the contents of various microprocessor registers and memory locations can be inspected and changed, and breakpoints can be set.
For testing and programming PCBs using boundary-scan, three basic elements are needed:
Boundary-scan controller (hardware).
Development software for creating test patterns.
The boundary-scan controller sends the serial data (sequence of test patterns) through the series strings. Various types of boundary-scan controllers exist which differ mainly in the speed with which data can be shifted through the strings and the number of strings that can be controlled in parallel. High-end, high-performance controllers shift the serial data at high speed, while cheaper, low-end controllers shift data at (much) lower speed. The performance of the controller has a significant impact when large amounts of data need to be shifted — often the case when programming flash memories.
The development software can often generate the necessary sequence of test vectors automatically. The net list of the board, the Boundary-Scan Description Language (BSDL), files for the boundary-scan devices, and optional models for the non-boundary-scan devices provide the input for the automatic pattern generation software (ATPG).
The net list describes which devices are present on the board and how the pins between these devices are connected. BSDL files describe the boundary-scan characteristics of a device. A BSDL file describes the order of the bits in the boundary-scan register and the instructions, and the codes that are supported by the device. The models for non-boundary-scan devices describe at least what the input and output pins of the chip are and how (some) output pins can be disabled to avoid bus contention. If such a model also describes the functional behavior of the device, then the automatic generation of a cluster test for this component can be generated automatically.
After the test patterns have been developed and validated by the test engineer using the development software, he (or she) can use these patterns in production — where the software provides the environment for testing. Now the operator can run the sequence of tests automatically. The production software can either be used as a standalone solution or may be integrated with other test equipment.
While test and in-system programming applications are mainly automated, the debug applications are more interactive. For these debugging, a boundary-scan controller is needed, along with specific interactive software for the debug application.
For software debugging, the application software provides the ability to inspect and set the contents of various microprocessor registers, memory locations and breakpoints. Next the processor can be started and halted in a controlled way to observe the operation of a program.
The application software for hardware debugging makes it possible to select pins of devices in the string to check the connectivity of two pins (continuity), to observe the value on a selected input pin, or to set values on specific output pins and observe which values are read by the connected input pins.
Boundary Scan provides a host of possibilities in the production line, and not just for testing PC boards. The system provides cost-effective methods of programming, as well as debugging products and systems.
Contact: JTAG Technologies, 111 West St. North #A, Easton, MD 21601
877-367-5824; fax 410-770-4774 E-mail firstname.lastname@example.org Web:
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