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Publication Date: 08/1/2010
ARCHIVE >  August 2010 Issue >  Special Features: Test and Measurement > 

Electrically with JTAG/Boundary Scan or Mechanically with ICT?
Test of a NAND gate using Boundary Scan.

Based on a proposal by the Joint Test Action Group (JTAG) some 15 years ago, the IEEE Std. 1149.1 became the basis of a revolutionary digital test technology for electronic assemblies named Boundary Scan or JTAG. For increasingly complex PCBs, Boundary Scan today is no longer an option, but has become a necessity. Increased component packaging complexity and density have already pushed In-Circuit Test (ICT) to its physical limits.

Conventional In-Circuit Test and JTAG/Boundary Scan are both purely electrical test technologies with the same underlying principles. The conductor paths (nets) are stimulated at one point and measured at another point. Information based on this measurement determine potential faults on a PCB. The main difference between Boundary Scan and ICT is their access to the nets. While the ICT needs to contact the tracks mechanically using a bed of nails, Boundary Scan is a purely electronic method that applies additional logic which is integrated into many complex components.

The In-Circuit Tester contacts the nets with probes using predefined test points. By using a complex matrix, the individual nets are connected with power sources — to stimulate the nets — and metrology for measuring the nets, requiring the use of a power source, a measuring unit and many relays to connect the nails, which finally contact the nets on the PC board.

With Boundary Scan technology, the levels (voltages) on the nets are driven and measured by the pins of the respective Boundary Scan component. The "Boundary Scan cell", assigned to a specific pin, decides whether a high or low level should be driven. The cell is situated between the component's logic and its physical pin allowing the use of the Boundary Scan cell as power source, metrology or both, saving additional external devices. Boundary Scan and ICT generate similar test results, in spite of their different configurations.

How Fast?
The faster the better, but how important is high test speed for minimal series? Because of the serial structure of the test bus, Boundary Scan is slower than ICT. The ICT executes test patterns in parallel which results in short test times. Indisputably, this is the big advantage of the ICT, but the disadvantage of the serial scanning is nearly offset by the newest Boundary Scan hardware generation such as Goepel's SCANFLEX® using a very high clock frequency.

Analog Components. Which test methodology covers analog components? Will resistors and capacitors be measured sufficiently? If a number of analog components are placed on a PCB, they certainly need to be tested. The ICT copes with it very well because it can fall back on a complex metrology.

Boundary Scan (IEEE Std. 1149.1), because it is essentially digital test technology, rarely understands the analog world (resistors can be checked for their presence but not for their actual ohmic value). The Std. IEEE 1149.1 is restricted to the purely digital connection test. But Std. IEEE 1149.4 is the foundation stone for extending Boundary Scan to the analog area, which is in the processing of establishing itself.

Digital Components. How about the test coverage of digital components? If predominantly digital assemblies are to be tested, the individual test technology's performance is of special interest.

Both test methods are predestined for digital technology. Unlike the ICT, Boundary Scan has two big advantages. First, extensive functional descriptions for highly complex components are not required. During the Boundary Scan, these components' pins are not controlled by the internal logic but exclusively by the Boundary Scan cells. Secondly, Boundary Scan does not need any backdriving unlike the ICT.

Net Contacting. Both hardware developers and test engineers have to solve the same problem: how to achieve the largest possible fault coverage?

This issue is linked to questions regarding the availability of the individual nets. Is there access to all important nets? For ICT there are several further questions: Where to put the test points? Are they too close to each other? Are there already too many test points on nearest space? Could the PCB be damaged?

There are serious mechanical considerations. A bed-of-nails adapter must be constructed, with nails positioned precisely, and each of the nails must be wired appropriately for the in-circuit tester. In addition, the system must be built in a way to open and precisely close the entire construction.

Boundary Scan works differently. Access is obtained through the components and the integrated Boundary Scan cells. Therefore, only four test bus signals need to be considered and wired into the tester — the only mechanical addition needed.

Flexibility. If the batch sizes are more than 100,000, the flexibility of the test technology is not as important as the prototype construction.

Obviously, the bed of nails adapter with its fixed, rigid nail positions is not very flexible. Layout changes mean considerable delays in terms of time and schedule fulfillment as well as additional costs because the adapters must be rebuilt. In some cases the test engineer only has to replace some nails, but in reality a new adapter is necessary. It becomes especially critical if the number of test points is higher than the number of measurement channels in the ICT. The laws of physics limit the number of nails per area for the vacuum adapter.

"Slimming" is the only solution, and this calls for combining with Boundary Scan. In contrast to ICT, the PCB layout is irrelevant. Tests are based on the netlist — the information regarding how the component pins are connected with each other. It does not matter where on the board they are. Moreover, the technology is not limited to a particular number of measurement channels.

Costs per new UUT. The costs for a unit under test (UUT) include the efforts for test program creation as well as the necessary test adapters. In terms of test program creation both test techniques are equal — assuming that the functional descriptions are at hand. Each test technology has its pros and cons. The differences in respect to adaptation costs are more significant. Costs for an extensive bed of nails adapter can about $15,000, whereas a simple plug connector is sufficient for Boundary Scan.

Costs for Test Equipment. Finally, there is the initial cost of the complete test equipment. Are ongoing costs to be expected? Is the price/performance ratio acceptable?

The ICT technology is based on a very extensive and complex metrology. A mature system can cost more than $150,000, whereas the complete hardware for Boundary Scan consists of a sophisticated "driver" for the four-wire test bus. The price for such a system is significantly lower than for ICT, but can vary widely depending on the software, needed performance and any extensions or expansions required.

Boundary Scan's advantages are critical, because they affect costs, flexibility and the future application of a given test technology. ICT just doesn't compare. Furthermore, Boundary Scan can be used at the design stage for programming and verification, for prototype testing, and later, for field service when needed.
Very complex contact carrier plate needed for ICT.

In the past, the needs of test engineers were not taken into consideration. While batch sizes may decrease, the variety of product continuously increases. PCBs are getting more and more complex and highly integrated packages such as BGA, µBGA, COB and Flip-Chip have become important major components on just about any PCB.

Placed side-by-side, ICT and its bed of nails compared to Boundary Scan runs up a huge list of shortcomings. In fact, if Boundary Scan did not lack the ability to test analog components, it would easily win the title "optimal test technology".

Since neither system can do it all, but both have particular advantages, the next step is to look at ways of combining both technologies. Analog components clearly require some form of ICT, while Boundary Scan excels in testing digital circuitry. Consequently, there is just one solution: Boundary Scan should be integrated into an ICT. This seems to be the "optimal test technology".

Testing the Digital Part
In using the combination "package", the digital part of the PCB to be tested is governed by Boundary Scan. Normally, this includes highly integrated packages and therefore, most of the nets. Test points are no longer required. The hardware designer will be happy and the costs for the bed of nails adapter will be significantly reduced as well. Some hundreds or even thousands of nails removed can make for a considerable cost reduction. Another positive: shedding the need for extensive functional descriptions for complex digital components.

The analog part of the PCB is tested with ICT. Because this includes simple and well-known components, the generation of test vectors should be minimized.

While the test coverage of this combination is close to that of the ICT, it is performed with significantly less effort for the test creation as well greatly reducing the time and costs for creating an adaptor (bed of nails).
Test of a NAND gate using ICT.

In summary, neither system is perfect. Both methodologies investigated have their pros and cons, although the Boundary Scan method's disadvantages are small when compared to ICT. A certain optimum can be achieved by combining features of both Boundary Scan and ICT.

With the ever-increasing level of outsourcing of mass production to countries with low production costs, the flexibility factor becomes more and more important. When searching for an appropriate test technology, the classic In-Circuit Test will lose its importance because it is much too inflexible and increasingly faces its limits due to its mechanical nature.

At present, Boundary Scan is mainly limited to digital circuits but further standards such as IEEE 1149.4 for analog applications as well as IEEE 1149.6 for dynamic signals are about to smooth the way for broadened acceptance. New standards such as IEEE 1532 for in-system programming of components blazes new trails for electrically testing PCBs — testing in ways that weren't used until now.

Contact: Goepel electronics LLC, 9737 Great Hills Trail, Suite 170, Austin, TX 78759 888-446-3735 or 512-782-2500 E-mail: Web: or

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