Save. Share. Connect.
Tuesday, May 24, 2016
VOLUME - NUMBER
PCB and Test
Test and Assembly
SMT and Assembly
Assembly and Production
PCB and Production
Assembly and Production
PCB and Assembly
Assembly and Packaging
PCB and Manufacturing
SMT and Production
Test and Measurement
Components and Distribution
Production and Packaging
HOME / CURRENT ISSUE
Test and Measurement
Add Message Board
Combining Boundary Scan and JTAG Emulation
Adding Emulation Test to Boundary Scan enables structural At-Speed test and improved diagnostics.
By Heiko Ehrenberg and Thomas Wenzel, Goepel electronic GmbH, Jena, Germany
Boundary Scan and JTAG Emulation are two perfectly complementary test methodologies, which are fused into one extremely flexible and powerful technique for advanced structural tests by Goepel electronics' VarioTAP technology. The coherent implementation of this technology in the company's SYSTEM CASCON environment makes possible a smooth integration of JTAG emulation tests into existing Boundary Scan projects.
Structural tests — detecting connectivity faults, such as open pins, solder bridges and shorts — have huge advantages for test automation, diagnosis, and deterministic fault coverage. However, in today's high-speed circuit environment, test coverage for dynamic failure phenomena demands higher test speed in order to carry out at-speed tests. For this, functional tests are more suitable, although test development effort is enormous and failure diagnosis is rather limited.
A single test technique that meets all requirements does not exist, and does not appear to be on the horizon. Instead a suitable mix of techniques appears to be the way to go. The combination of Boundary Scan and emulation test can be considered as a particularly promising approach.
Boundary Scan and Emulation Test
The basic idea of emulation tests is not new; in fact, it was successfully used and supported with device-specific tools since the early 1980s. Processor specific Pods, inserted into the Device Under Test's (DUT) socket instead of the actual device (e.g. a microprocessor), were used to take over control of the printed circuit assembly's (PCA's) system bus. Bus emulation tests provided testability of all connected components, including peripheral interfaces. The same technique was also used for software verification in the form of In-Circuit-Emulators (ICE).
However, decreasing physical access and increasing clock rates called for new concepts. Today, device emulation is done with on-chip emulation circuitry, also known as On-Chip Emulators (OCE). Besides proprietary interfaces, the JTAG Test Access Port (TAP) defined in IEEE Std. 1149.1 is often applied as a communication port.
Another standard defines a debug interface that utilizes the TAP, however, in practice we find various implementations of JTAG emulation ports. The fascinating aspect of this solution is that the DUT core can be controlled over just 5 wires, potentially without any additional external hardware resources, and without loss of performance. This benefit can be exploited in JTAG TAP controlled emulation tests.
Emulation Tests can be considered as classic Functional Tests, and therefore have the same advantages and disadvantages. A combination of both techniques — Boundary Scan and Emulation Test — seems absolutely reasonable, however system solutions must exploit the synergy between both methods. In this regard, Goepel electronics' VarioTAP technology offers new possibilities.
Fusion of Tests
An examination of previously available system solutions involving Boundary Scan and Emulation Test provides us with classification in three performance groups:
The first two classes differ in the capability — or lack thereof — of using consistent hardware and software for the test execution. A loose combination of Boundary Scan and Emulation Test tools requires separate hardware and software tools — typically device-specific software and JTAG pods are required for Emulation Test. A hybrid integration can utilize the same JTAG controller hardware, and possibly even the same software for both Boundary Scan and Emulation Test. The test generation for Boundary Scan and Emulation Tests, however, is carried out separately, in both classes. Therefore, the potential of each method is not fully developed, since a Boundary Scan test will not become more dynamic, nor will an Emulation Test become more structural or provide better diagnostics.
As the first representative of the third category, VarioTAP views Emulation Test from the same perspective as Boundary Scan, providing test access utilizing design integrated pin electronics.
The internal architecture for Boundary Scan TAP includes: static pin electronics; BScan cells define vectors; serially controlled pin interface; scalable number of pins; arbitrary static signal timing; arbitrary vector definition per pin.
The internal architecture for JTAG Emulation TAP includes: dynamic pin electronics; microprocessor defines vectors; parallel controlled pin interface; fixed number of pins; rigid dynamic signal timing; vector definitions only possible for address and data bus. With this approach, the VarioTAP software tools allow the control of dynamic emulation pin electronics at the same vector level as static Boundary Scan pin electronics. Thus the handling of Emulation tests seamlessly merges with the familiar handling of Boundary Scan tests, allowing direct interactions between Boundary Scan and Emulation Test as one element of the complete fusion.
The second element enabling this fusion is the adaptive streaming technology of VarioTAP, allowing simultaneous control of both types of pin electronics.
With the tool suite available for Automatic VarioTAP Test Program Generation (AVTG), predictable fault coverage and pin level diagnostics are possible. In addition, VarioTAP applications can be written manually in the CASLAN programming language. The AVTG tool for Memory Access Test, for example, uses structural test vectors and associated diagnostics similar to Boundary Scan based Memory Cluster Tests for the dynamic test of (dynamic high-speed) RAM. In this manner, a total fusion of Boundary Scan and Emulation test is achieved on the basis of a uniform software and hardware platform, paving the way for the application of advanced structural test strategies.
Clearing the Hurdles
Emulation Test via VarioTAP extends the test coverage for current designs significantly beyond what can be achieved with pure Boundary Scan.
Significant improvement of the test program quality with higher fault coverage and shorter development time.
At the same time, VarioTAP simplifies some critical DfT (Design for Test) requirements such as clock controllability, and enables fast Flash programming. Emulation Test is very effective and can fundamentally improve the quality of test, especially for testing highly complex non-scannable analog and digital circuitry, as well as highly dynamic structures.
As a result, VarioTAP overcomes in principle the limitations listed both for Boundary Scan and for conventional Emulation Test. Based on the technical features and the fact that VarioTAP can interact not only with Boundary Scan but also with external test instruments, we see a multitude of essential benefits and new opportunities:
Deterministic test coverage aids definition of optimal test strategies.
Highest productivity with automated test program generation.
Advanced structural test with pin level diagnosis.
No device-specific diagnostics software or firmware needed.
Uniform system platform with fully integrated tool suite.
Single language for control of both Emulation test and Boundary Scan test.
Simultaneous debugging of Boundary Scan and Emulation vectors.
Support for devices featuring on-chip emulation by VarioTAP model library.
Fast programming of embedded or external Flash memory.
Multi-TAP and multi-core support including in-system emulation.
No need for device specific knowledge or tool chain.
Applicable as stand-alone system or integrated in ICT, FPT, MDA, FCT.
As VarioTAP does not require invasive test probes and is controlled only by the TAP signals, it can be utilized throughout the whole product life cycle.
Prototypes can be tested faster and more exhaustive (Rapid Prototyping).
Software developers can save the time to write special diagnostic routines.
Concurrent engineering of design and test is possible.
Allows hierarchical test at the SoC, board, and system level.
Cycle time for New Product Introductions (NPI) can be reduced.
Production tests provide better test coverage and become more cost-efficient.
Fewer test points and probes needed for ICT reduce fixture costs.
Shorter repair times due to improved diagnostics.
Lower "bone pile" with "dead" or "No Failure Found" boards.
Higher efficiency of field service applications.
While standalone test systems are widely used in test labs, a mix of different test techniques is still recommended for the production environment. Various aspects need to be considered when defining a suitable test strategy. One of the most interesting strategies is the combination of Boundary Scan and VarioTAP with Flying Probe Testers. The Flying Probe Tester can test the analog circuitry, and then Boundary Scan/VarioTAP can utilize the probes as virtual Boundary Scan pin(s) for the extended Boundary Scan tests and for more precise diagnosis.
The development of Emulation tests is based on the same project data that is used for Boundary Scan, with access to the same auxiliary tools, such as device library, multi-mode debugger, test coverage analyzer, or ScanVision — for the graphical display of layout or schematic features, or visualization of detected faults.
In addition to the VarioTAP tools, one element plays a crucial role — the VarioTAP model. These models are structured as modular Intellectual Property (IP) and provide a behavioral definition of certain microprocessor functions used in different VarioTAP applications. We differentiate these VarioTAP applications: Flash programming, Bus Emulation Test (BET), and System Emulation Test (SET). Essentially, respective device models are to VarioTAP what a BSDL file is to Boundary Scan.
The number of IPs, including custom IP, in a single VarioTAP model is not limited. Furthermore, it is possible to simultaneously control several different Micro Controller Units (MCUs) on a Unit Under Test (UUT), since multiple VarioTAP models can be active at the same time. On the tester hardware side, Goepel's SCANFLEX platform provides up to 8 independent TAPs. In the case of multi-core applications, the number of cores is theoretically unlimited. By combining the benefits of both methods, VarioTAP provides a significantly higher test quality, shorter test and programming times, and higher quality of diagnostics with considerably reduced costs. The modular software IP based architecture, makes VarioTAP completely independent of the target processor(s) and prepared for future applications and standards.
Contact: Goepel electronics LLC, 9600 Great Hills Trail, Suite 150W, Austin, TX 78759
512-782-2500 E-mail: firstname.lastname@example.org Web:
© 2015 USTECH. All Rights Reserved. |
Contact Us: 610-783-6100 | email@example.com
powered by GIM