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A New Approach To Component Stacking
Technician examines sheet of developmental embedded die. (Photo: Fraunhofer IZM.)
By Keith Gurnett and Tom Adams
One of the most innovative concepts in electronics assembly is the idea that both active and passive devices can be moved from the surface of the printed wiring board to new locations inside the board itself. The concept has existed for decades, but is now being given new life by two groups, one European and one American.
The European group is a consortium consisting of Fraunhofer IZM, the Technical University of Berlin, and several commercial firms. The American group is a California company, Verdant Electronics, headed by Joe Fjelstad. Verdant has agreements with a number of firms for development of the technology.
The European consortium, which used the acronym HIDING DIES (www.hidingdies.net) for its most recently completed project, has nearly a decade of experience in the assembly techniques needed to put active and passive devices inside the board. The key steps are these:
While still in wafer form, the contact pads on the die are modified for PCB metallization.
The wafers are thinned, generally to 50 microns, and diced.
A board core, which may be as thin as 150 microns, is used as the starting point for the board.
The die are adhesively bonded onto the board core. Bonding is carried out by an ordinary die bonder with emphasis on making the bond and the die very flat. One Fraunhofer rule is that all processes must be suitable for existing assembly equipment.
Passive components are adhesively bonded to the board core.
A layer of Resin-Coated Copper (RCC) is placed on top to form a build-up layer. The resin is 70 microns thick (vs. 50 microns for the die), and the copper 5 microns thick. During curing, the resin conforms to the die, and the surface of the copper comes out flat.
A laser is used to drill microvias through the cured build-up layer down to the contact points on the components. The microvias are then plated with PCB-compatible copper.
A patterned layer of resist is laid down on the copper surface, and an etching process creates the traces.
A key feature of the Fraunhofer method, which is called "Chip In Polymer", is that the board core, the bare die, and the build-up layer are all very thin. Many passive components have in recent years shrunk their dimensions to the point where they are currently almost small enough to fit into a Chip In Polymer design.
A Different Process
The much newer Verdant method, known as the Occam Process, differs in some respects. It begins with a board core, bonds components to the core, adds a build-up layer and forms traces on top of the build-up layer. One significant difference is that the active components are packaged devices, typically chip-scale packages (CSPs) that would be much thicker than the 50-micron bare die that Fraunhofer uses. The board core is also likely to be thicker, and may serve as a heat spreader or as a shield. Vertical path pin vias may be incorporated to connect the two faces of the assembly, and a redistribution layer can be added ? both features that facilitate the stacking of components. Overall, there is less emphasis on compactness in the Verdant method, although there is nothing to prevent a participating company from using thinner geometries. In both methods, the end product bears little resemblance to a conventional printed circuit board.
Shorter Connection Distances
In both methods, one of the driving forces behind building the board up around the components is that connection distances become much shorter and performance therefore improves. Another benefit is that no solder is used in assembly, and no reflow oven. And the resulting systems, with their components and connections locked in epoxy, are likely to be very durable.
Both methods can also be used to arrange the die on top of each other, by placing additional build-up layers on top of the original build-up layer. In this way it would be possible to wind up with a stack of active components. A "board" might simply be a substrate slightly larger than the area of a given die, with a stack of die built up on the substrate — a new way of making a stacked die package without wires and without solder.
Cross section of layered die.
It would be somewhat similar to stacked-chip packages currently being produced, but the higher connection speeds, lack of solder and freedom from reflow might make it superior in both performance and reliability.
Both Chip In Polymer and the Occam Process could be used to stack die in this novel fashion. Fraunhofer physicist Andreas Ostmann explains that a die stack can be made in one of two ways with Chip In Polymer. Because the initial substrate is a thin copper foil, a two-die stack can be created by mounting die back-to-back on opposite sides of the foil.
Alternately, he says, all of the chips can be stacked on one side of the substrate, with a build-up layer, microvias, and traces for each layer. This method of stacking die has already moved beyond the concept stage, and will be used in the Hermes project, which began on May 1, 2008 and which focuses on moving the buried die concept into real-world production. One of the items already planned under Hermes is the assembly of 4-chip stacks of this type.
Would a Chip In Polymer stacked die configuration be less expensive to assemble than a conventional stacked die package? For something like a wire-bonded stack of the type currently used for flash memory, Ostmann thinks that the Chip In Polymer probably would not be cheaper, because the method currently in use is well established. But for more complex die, embedding the die to make a stack has some real advantages, and the fact that Chip In Polymer works with existing assembly equipment might make it less expensive than conventional stacked-die packages.
Using somewhat larger dimensions, the Occam Process can achieve similar results, and perhaps — because conventional chip-scale packages are being used — with inherently lower costs. Joe Fjelstad reports that commercial products as well as test vehicles for military and scientific applications are in early design stages.
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