Wednesday, June 20, 2018
Publication Date: 12/1/2008
Archive >  December 2008 Issue >  Business News > 

Pac Tech Grand Opening for New Asian Facility
Formal ribbon cutting (left to right): Ghassem Azdasht, CTO, Pac Tech GmbH; Dr. Elke Zakel, CEO & President, Pac Tech Group; Tuan Lim Guan Eng, Chief Minister of Penang; Hiroshi Nagase, President, Nagase & Co., Ltd, Tokyo; and Dato Lee Kah Choon, President, Invest-in-Penang Berhad.
Santa Clara, CA — Pac Tech Packaging Technologies has opened its new Pac Tech Asia facility. The new 55,000-ft.2 facility located in Penang, Malaysia. The opening celebration was attended by the Chief Minister of Penang, a number of local government officials, business leaders, engineers and managers from some of the world's leading electronics companies.

In conjunction with the opening celebrations, the company also conducted an advanced packaging technical symposium. The symposium included a full day of presentations on both business and technology trends within the packaging industry, including WLCSP, flip-chip, and 3D packaging. Over 200 people from around the world attended the symposium. Based on the success of this event, the second of what is hopped to be an annual symposium is being planned for next year. Next year the format will expand to include additional topics related to wafer-level packaging trends and applications. The new facility is designed to encompass advanced production floor space, including cleanroom area. Both are equipped with the latest generation equipment for 300mm wafers. There is 55,000 square feet of state-of-the-art wafer bumping, electroless nickel and gold under bump metallization, wafer sawing, wafer thinning, die sorting and assembly equipment and backend processing capabilities for semiconductor companies within the Pacific Rim.

The new facility is designed and laid-out to accommodate prototyping and mass-production quantities up to 600,000 wafers per year. Pac Tech Asia will provide a variety of special applications designed to enhance and support the Asian semiconductor manufacturing community. The applications supported will include: electroless Ni/Au under-bump metallization for copper and aluminum devices, solder-paste stencil printing for flip-chips, solder-ball placement for wafer-level CSPs down to 200µm ball diameters, and micro solder-ball placement for fine-pitch applications down to 80µm.

Contact: Pac Tech USA Inc., 328 Martin Avenue, Santa Clara, CA 95050 408-588-1925 or Pac Tech Asia Sdn. Bhd., Plot 14, Medan Bayan Lepas Technoplex, Phase 4, Bayan Lepas Industrial Zone, 1190 Bayan Lepas, Penang, Malaysia +60 4 644 103 Web:

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