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Tuesday, February 20, 2018
VOLUME -23 NUMBER 8
Publication Date: 08/1/2008
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Special Feature: Test and Measurement
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August 2008 Issue
Special Feature: Test and Measurement
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The Real World of Boundary-Scan Testing
A complex BGA part has undergone a test with ICT and has failed. The fault is actually an open pin on a control line which prevents the device from functioning according to the ICT model. However, it cannot be precisely diagnosed as such, so the device is removed and discarded. A new device is fitted, all works correctly and the rework sheet is marked with "Faulty BGA part replaced". If the faulty BGA part was boundary scan compliant then a boundary-scan interconnect test would likely have identified the fault as a net "stuck-at 0/1" fault or an "open pin fault" — more accurate but requiring a degree of interpretation before the fix could be applied. However, with JTAG Visualizer the faulting net is easily seen (highlighted in red) and the "fix" could simply be an isolated reflow of the area around the BGA, thus saving the cost of the part and enabling a speedier repair.
By Ray Dellecker, Marketing Manager JTAG Technologies, Stevensville, MD
It's no secret — everybody has noticed the uptake in JTAG/boundary-scan test technology over the past 10 years or so. However, in spite of the avalanche of articles describing the technology and outlining the on-paper benefits, there are still relatively few engineers around who have spent much time and have had the real experience to run boundary-scan tests and examining/interpreting the results.
In the mid 80s, ICT engineers and test professionals concluded that surface-mount packaging technology would drastically affect traditional test methods. These were methods that had been used for at least the previous 10 years to detect faults on devices (typically 7400 series and other discrete logic components) mounted on PC boards. ICT was popular as it could, and still can, test individual parts for functionality by quickly driving test patterns across the device using high (>200mA) current test pins that probed the through-hole connection pins of the device(s) under test. A failed device could be spotted and replaced. However, what if the packaging meant that it was no longer possible to probe the pins directly, because they were surface mounted? Worse still, what if the packaging meant that complex parts could not easily be modeled by the ICT engineers?
These were questions that prompted the formation of the JETAG and subsequently JTAG (Joint Test Action Group) committees to look at ways of solving this test conundrum. What they came up with is the now ubiquitous boundary-scan architecture that embeds test circuitry into medium- to high-complexity ICs such as PLDs, Micros and ASICs. Moreover, by the time the boundary-scan architecture was ratified as IEEE std 1149.1 it was also realized that most test problems were not in fact related to malfunctioning parts but were more often due to assembly process faults: reversed parts, lifted pins, poorly reflowed joints etc. This "shift" was partly due to the fact that silicon yields had increased, leading to increased IC reliability, and also partly due to the fact that 100 percent test was applied to silicon parts rather than simply testing a sample from each batch. Subsequent analysis has shown that for today's designs up to 99.7 percent of faults lie not with the devices but with assembly or process errors.
Test Industry Response
Given this information how would or how should the test industry respond to the changing test challenge? The candid answer to this question would be "slowly". The behemoths of the test industry would suggest that ICT testing is still relevant for all designs and for good reason — future sales of large, costly test machinery. Others embracing new technology such as boundary-scan are able to take a different approach although that takes us to the next question: If JTAG/Boundary-scan is such a good idea then why has market acceptance been (relatively) slow and the market for ICT machinery is still (relatively) buoyant?
The answer, as always, is resistance to change. Few people really like change and many are positively hostile towards it. This means that if it is possible to squeeze more life from traditional test techniques then JTAG/boundary-scan can often be shelved until "absolutely necessary". What's more, the resistance to change motive has played into the hands of the ICT vendors. Diagnostic reports in these machines still refer to "faulty devices", making it easy to fix the fault by device swapping — in spite of the fact that this may not be the root cause. Often it is the symptom that is addressed and not the cause.
Net vs. Device
While ICTs still mainly produce a "device-oriented" test report, boundary-scan, by the nature of its operation, produces chiefly a "net (or interconnect) orientated" test. Of course with today's boundary-scan tools, it is also possible to test non-boundary-scan elements (buffers, decoders, memories, communications devices etc.) that can be accessed by the boundary-scan resources, but once again the object here is not necessarily to fully and functionally exercise a part, since the serial-to-parallel nature of JTAG/boundary-scan is not conducive to very large test vector (pattern) sets.
JTAG Visualizer highlights faulting nets and enables test engineers to see the most likely circuit areas that could cause a failure.
A further problem arises when a device suffers a catastrophic failure spawning multiple faults. Take the example of a poorly fitted BGA device, perhaps on a board that has warped during reflow and an entire corner of the part has "lifted". The resultant diagnostic report from a JTAG test system may list dozens of open circuit faults which could be bewildering to the test technician more familiar with the "change ICx" type of fault report.
Faced with this type of reporting, two possibilities exist. The first is to train the technician in the "ways" of boundary-scan. With some working knowledge of how boundary-scan tests are implemented, technicians and engineers can work back from the fault report and refer to schematic information to assess the cause of the symptom. This has hitherto been the preferred route, however the escalating use of off-shore manufacturing facilities with the associated communications difficulties has spawned other options. The second option is to use a graphical layout viewer package such as JTAG Visualizer to highlight faulting nets and see the most likely circuit areas that could cause a failure.
It is clearly evident that the use of integrated layout graphics combined with fault report information from a boundary-scan system can add much to the efficacy of this test method. In many complex digital designs it is easily the best "bang for buck" when compared to traditional methods.
However integrated solutions that include JTAG/boundary-scan within functional test or ICT will still be relevant for many lower-tech designs or those with a predominantly analog content.
Contact: JTAG Technologies, 1006 Butterworth Ct., Stevensville, MD 21666
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