HOMECURRENT ISSUEARCHIVETech XchangeABOUT USSUBSCRIBEMEDIA KIT中文
Login


Electronic Mfg. Products
Search :      Wednesday, January 07, 2009


U.S. Tech Part Search



Powered by


Terms Of Use

 

 

 

 

 

Endicott: SiPs Reduce PWB Size
2-sided SiP.
Endicott, NY — System in Package (SiP) designs from Endicott Interconnect (EI) Technologies reduce size and weight, eliminate multiple packages from a printed wiring board (PWB) by combining them into a SiP for improved electrical performance, while reducing PWB complexity and cost. The result is a significant shrinkage in package size and an enormous expansion in performance per sq. in. of PC board real estate.

The company can use its SiP technology to achieve reductions in PC board real estate up to 27x less than that of the original PC board. This is accomplished by replacing many of the packaged components with bare die and combining the company's experience in thermal solutions with its PTFE-based HyperBGA® or CoreEZ™ organic semiconductor packages with thin core build-up flip chip technology. These semiconductor packaging solutions reportedly offer very good electrical performance, wireability and reliability.

For example, a 7.75 x 15-in. PC board can be re-designed to a 2.2 x 2.2-in. size using a 3-4-3 CoreEZ substrate with 4 signals, 6 planes and 30µ lw/ls, and an assembly that includes 5 flip chip FPGAs, CSP memory, passive components, SMT components, PGA connector and 2-sided assembly.

Another SiP conversion using reduced package size components and CoreEZ technology has condensed a single-board computer (SBC) design from 25-in.2 to 9-in.2.

Also, these SiP designs are not physically limited to a square or rectangular shape, should the application call for something round or otherwise "out of the box".

For more information, contact Endicott Interconnect Technologies, Inc. 1093 Clark Street, Endicott, New York 13760 866-820-4820; fax: 607-755-7000 Web: http://www.eitny.com

 

search login