Save. Share. Connect.
Sunday, May 27, 2018
VOLUME -22 NUMBER 6
Publication Date: 06/1/2007
Front Page News
People in the News
Contract Mfg. Products
Test & Measurement
Product Preview: Atlantic Design/MDM
June 2007 Issue
Test & Measurement
Add Message Board
Testing Times for Lead-Free Alloys
A tin/lead coating comprises three layers sitting on the pad substrate. The top layer is an oxide that must be stripped away by the flux prior to soldering; otherwise wetting will be poor.
By Graham Naisbitt, Managing Director, Gen3 Systems, Farnborough, UK
Removing lead from electronics may be a good idea, but the transition to lead-free solder dramatically changes the electronics assembly procedure, particularly for high-reliability products. Tin/lead solder joints have been comprehensively characterized over many decades, and manufacturers of products for safety-critical or life-dependent applications are able to reassure end users of their reliability.
The task of fully characterizing lead-free solder joints becomes doubly important when one considers that consumers might not feel so comfortable about moving quickly to substitutes if they realized there could be lingering doubts about lead-free reliability; especially if their lives depend on lead-free electronics such as being a passenger on a commercial aircraft or in a vehicle equipped with an airbag.
To lower the probability of failure, manufacturers routinely test component and PC board pad solderability. Without good solderability — a measure of how well molten solder wets component joints and PC board pads indicating the robustness of the surface finish — the likelihood of forming a reliable solder joint is dramatically diminished. Joints exhibiting poor solderability may still form a solder joint and even pass final electrical test. But the likelihood of failure due to stress, heat or vibration is high, and this is unacceptable in a life-or-death application.
But the change to lead-free soldering — with its narrower process window — has exposed deficiencies in traditional test methods used to establish solderability such as "dip-and-look". In this test, a representative component is dipped in molten solder and the height that the meniscus climbs is observed to gauge solderability.
Component manufacturers and PC board makers prepare their devices for soldering by applying one of several surface finishes to the device terminations and pads on the board. Examples of surface finishes are organic solderability preservatives (OSPs), immersion tin and immersion silver, electrolytic and electroless nickel/gold, and fused or hot air-leveled solder.
These surface finishes are designed to both protect the terminations and pads prior to assembly, and then provide a surface that encourages wetting by the solder during the reflow or wave solder operation. While the PC board finishes are subject to some standards such as IPC-4552, 4553 and 4554, the finishes on the component terminations are not. Although each surface finish has its merits, it is generally agreed that solder is the best finish when fusing to solder paste or to itself.
Unfortunately, all surface finishes are subject to a degree of degradation. And that degradation is influenced by factors such as storage conditions and times. The UK's National Physical Laboratory (NPL), for example, has conducted extensive studies into "solderability aging" and the mechanisms of degradation.
A tin/lead coating comprises three layers sitting on the pad substrate. The top layer is an oxide that must be stripped away by the flux prior to soldering; otherwise wetting will be poor. The second layer is the fusible coating that encourages good wetting, and the final layer is an intermetallic created by an interaction between the copper in the substrate and the tin from the fusible coating. If the fusible coating is too thin or porous, it will be consumed by oxidation allowing oxygen to reach the intermetallic layer. Once the intermetallic layer oxidizes, wetting can't occur. The mechanism that causes solderability degradation is the thickening of the oxide and intermetallic layer. The rate of this growth is influenced by storage factors such as humidity, temperature and time. Solderability decreases as a function of aging.
Solderability, Not Soldering Ability
Experienced manufacturing engineers are well aware of this failure mechanism, and routinely take steps to determine if their components and PC boards are still satisfactory prior to assembly. However, the methods they use to test whether solder joints will last the life of the product have been called into question by the migration to lead- free alloys and the IPC's and IEC's comprehensive testing. To make matters worse, there is an industrywide lack of understanding as to what attribute is actually being tested.
The problem is that manufacturers often fail to draw a clear distinction between solderability — how well molten solder wets — and soldering ability — a term used to describe how well a specific combination of flux and solder work together to ensure that a component is soldered to a PC board. They are not the same thing. It's important to note that a device with "unacceptable" solderability (according to the standards) can often still be soldered with the "right" combination of flux and solder. For example, manufacturers can compensate for poor solderability by increasing flux volumes during production thus improving the soldering ability of the assembly. But that's no longer an option when using lead-free alloys for two reasons:
The much narrower process window for lead-free soldering is less forgiving of process changes during production, increasing the likelihood of forming a suspect joint.
Additional flux has a detrimental effect on board cleanliness, particularly one assembled using a no-clean process. As the flux volume increases on a standard test coupon, there is a drop in surface insulation resistance (SIR). Electrically conductive areas of the board are formed by the flux residues after evaporation of volatile components. These conductive areas could contribute to medium- and long-term board failures.
The IPC's and IEC's analyses have established that the most important criterion for ensuring that lead-free soldering produces high integrity interconnections — while maintaining tight process control and limiting potentially failure-inducing contamination — is "acceptable" solderability.
Although soldering ability testing does have a place for qualitatively checking if process flux and solder alloy are working well, it's not scientifically controllable enough to form the basis of a benchmark standard for solderability testing.
Choosing the Best Test Method
So how do you ensure you are measuring solderability rather than soldering ability for a lead-free assembly process? To answer this question, the IPC committee agreed to undertake a "round-robin" test program to study the characteristics of lead-free alloys and fluxes. The round-robin tests looked at:
The standards, which are expected to be published soon, will also formally clarify the difference between solderability and soldering ability. The standards will define a process for solderability testing that precisely specifies the test equipment, how the test should be conducted, and the materials to be used to ensure good Gauge R&R.
For example, for a precision solderability test it is recommended that the test flux is carefully maintained and kept free of contamination during measurement (see IPC J-STD-002C sections 188.8.131.52 and 3.5.2). This includes either covering the flux when not in use and discarding it after eight hours or maintaining it to a specific gravity of 0.843 ±0.005 at 25°C ±2°C (77°F ±3.6°F) and discarding it after one week of use.
Furthermore, the solder in the solder bath used for solderability testing should also be chemically or spectrographically analyzed or replaced each 30 operating days according to strict standard-defined contamination limits. This includes the composition of the lead-free solder (including maximum contamination levels) being maintained during testing with the silver and copper element levels adjusted for alloy requirements.
It's easy to see that this isn't a regime that can be maintained using flux and solder from day-to-day production.
Fixture typically used for dip-and-look testing.
But what of the test methodology itself? Is the decades-old dip-and-look test method formalized in standards such as J-STD-002 and 003 an acceptable solution?
In this test (which is well defined), technicians dip representative component samples into a molten solder bath and observe how far the meniscus climbs. With experience, this provides a qualitative measure of solder wetting and hence solderability. The method is also quick, easy and cheap to implement.
The major problem with dip-and-look, however, is that as a test method it exhibits poor Gauge R&R. In other words, even if the materials used for the test are strictly controlled (as required by the new standards), two people conducting the test at different times are likely to interpret the results differently. What kind of basis is there for quality control of lead-free assembly if one person says the component and/or bare board is fine but another says it's not, depending on the time and place of the test?
Force Measurement Recommended
So, what's the alternative? According to the IEC: "(We recommend) wetting balance force measurement and globule testing and we are attempting to harmonize standards documents, to provide acceptable Gauge R&R to its defined methodology."
Solderability measurements using a wetting balance are able to measure force to an extremely high level of accuracy — to a resolution of milli-Newtons. Some electronics-based instruments even measure to levels of better than 1µN/Bit. Although the type of wetting balance used for plated through-hole (PTH) and surface mount (SM) components differs, both are based on the same physical principles.
If a metallic body is dipped into molten solder, the weight and speed with which the solder meniscus climbs upwards on the body's immersed surface indicates how well the solder wets it and thus its solderability. The greater the solderability, the higher the meniscus will climb and that can be measured as a change in the vertical force action on the suspended specimen.
For certain thru-hole components and circuit board coupons, the specimen device is immersed in a bath of molten solder and the forces of buoyancy and surface tension action upon it are measured. For smaller SMDs, a higher resolution method is required: the microwetting balance procedure that employs a solder globule. Here the solder bath is replaced by a globule block of 4-, 3.2-, 2- or 1mm size employing 200-, 100-, 25- or 5mg pellets of solder alloy — depending on specimen size — allowing the individual leads of a multi-leaded component to be tested.
Time for Change
The introduction of lead-free has disrupted a process — assembly using tin/lead solder — that has been characterized over many decades. One effect is that the IPC and IEC have determined — after extensive examination involving over 30,000 tests — that traditional test methods and process corrections are no longer sufficient to determine the reliability of lead-free joints. New methods and clarifications of the difference between solderability and soldering ability are due from the organizations before the end of this year. These are likely to conclude that solderability testing is essential for manufacturers wanting to underwrite the integrity of their high-reliability products. Moreover, the standards will conclude that solderability testing should be based on wetting balance force rather than dip-and-look. This former method will ensure a quantitative measure of the robustness of a given surface finish under test, with acceptable Gauge R&R while removing any scope for opinion or "manual" judgment calls that typically occur with dip-and-look.
For more information, contact: Gen3 Systems Limited, Unit B2, Armstrong Mall, Southwood Business Park, Farnborough, Hampshire, GU14 0NR, U.K.
+44 (0) 12 52 52 1500 Web:
© 2015 USTECH. All Rights Reserved. |
Contact Us: 610-783-6100 | firstname.lastname@example.org
powered by GIM