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Shrinking ICs Fit 3D Packaging
Xilinx is now working on its second generation of SoCs and 3D ICs, as well as its next-generation FPGAs.

Designing integrated circuits (ICs) in a vertical rather than a horizontal direction has long offered the promise of smaller chips with highly integrated functionality and less power consumption in a single package compared to several devices in several packages. Yet, the design and manufacturing of three-dimensional (3D) ICs and their packages has never been easy. It poses many challenges, faced by device and package developers, by engineers assembling test solutions for 3D ICs, and even for the writers of electronic-design-automation (EDA) software for simulating the performance of these 3D ICs under different conditions. Still, with growing demands for numerous smaller ICs, such as microprocessors and sensors, the electronic industry is seeking ways to not only make these 3D ICs smaller and more reliable, but more cost effective as well.

Of course, as markets for portable electronic products, such as smart phones and tablet computers continue to expand, 3D ICs are also being targeted as solutions for achieving smaller end-product sizes at lower operating power consumption and, hopefully, at lower manufacturing costs. As electronic products continue to boost capabilities in smaller housings, the need increases for such devices as microprocessors with enhanced memory capabilities, and such devices can save space when multiple microprocessor and memory circuit layers can be "stacked" in a vertical direction, rather than spread out along a semiconductor wafer in a horizontal direction, in the manner of flip-chip devices.

These 3D ICs are being planned as replacements for multiple-function system-on-chip (SoC) devices which integrate multiple components and their functions onto a single silicon die which is then housed within a single package. An SoC, which may include a microprocessor, digital logic, memory, and additional components, may have hundreds of millions of gates and operate at gigahertz rates. Fabricating these different functions on the same die can be challenging for any process. In addition, having analog and digital components in close proximity can lead to noise problems, and the costs of developing and testing these SoCs has been rising, leading to increasing interest in 3D ICs.

One of the more critical features in fabricating reliable 3D ICs is the interconnection between layers. Of course, not all 3D devices are fabricated from multiple layers on a single chip. In some cases, 3D devices are formed by means of system-in-package (SiP) technology, where multiple ICs are stacked and interconnected within a single package. The vertical design approach is similar in both cases, with shorter interconnections required between device layers or separate ICs than compared to a horizontal approach. The shorter interconnections resulting from the vertical design approach exhibit less parasitic capacitance and require less power than the longer interconnections of a horizontally designed, planar approach.

Heat buildup within densely packaged 3D ICs is also a concern. Although the shorter interconnections in a 3D IC should amount to less power consumption and heat dissipation per interconnection than in a planar device design, the greater number of interconnections and higher density of those interconnections in a 3D IC package requires effective dissipation of heat from within the IC package. Silicon die have generally been attached to SiP substrates by means of two-dimensional (2D) wire-bond or flip-chip. But 3D ICs typically incorporate a silicon interposer substrate to enable fine die-to-die interconnections; this substrate often includes through silicon viaholes (TSVs) to provide connections from upper metal layers to backside metal layers, to support heat flow. The TSVs are essentially copper via holes with diameters ranging from 1-30µm.

The concept of a 3D IC is fairly simple, of positioning die to occupy vertical rather than horizontal space, but designing and realizing a 3D IC can be considerably more difficult than working with 2D ICs, perhaps the main reason that 3D IC technology is slow to see adoption in the industry. A number of IC suppliers have promoted their efforts and products in 3D IC technologies, including Xilinx ( and Altera ( Both offer products based on stacked die within compact housings. In fact, Xilinx uses its stacked silicon interconnect (SSI) technology within its programmable 3D IC products for improved logic density and bandwidth compared to planar 2D monolithic designs. The firm claims that field-programmable gate arrays (FPGAs) and transceiver mixed-signal die are integrated with more than 10,000 programmable interconnects within their packaged FPGA products through a silicon interposer as part of the SSI technology.

As these 3D ICs scale down in dimensions to line widths of 20nm and less, the package remains an essential part of protecting the circuitry from the outside world and, at the same time, providing reliable electrical interconnections to the circuitry within the package. For the most part, 3D IC circuit designs are planned for use with conventional housings, including quad-flat-no-lead (QFN) packages, ball-grid-array (BGA) packages, and small-outline-transistor (SOT) packages. But the complexity of 3D ICs often calls for more elaborate packaging solutions, including embedded-die approaches and fan-out wafer-level chip-scale packaging (WLCSP) approaches. Especially for the high pin counts that inevitably result from 3D IC designs, WLCSP housings are becoming more standardized and used with circuit designs requiring 100 or more package pins and even more complex 3D IC functions within, such as microelectromechanical-systems (MEMS) circuits. The use of TSVs within these packages enables the coexistence of different types of circuit functions on the different 3D IC layers.

Forging the Future
A growing number of commercial semiconductor foundries currently offer 3D IC fabrication capabilities, including Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC,, GLOBALFOUNDRIES (, TowerJazz (, and IBM Microelectronics ( Some of these foundries, such as TowerJazz, work closely with packaging specialists such as Interconnect Systems, Inc. (ISI, on providing advanced 3D packaging solutions for IC developers. In addition, organizations have formed to provide help for 3D IC designers. For example, the 3D IC Community ( supports the 3D IC design and development community with a centralized collection of news, blogs, and white papers on the topic, while the 3D-IC Alliance ( has been formed to support firms involved in the design and manufacture of 3D ICs.

However, advancement of 3D ICs will depend on two supporting functions: computer-aided-engineering (CAE) software tools with accurate models capable of simulating the performance and behavior of 3D ICs under a wide range of operating conditions, and test systems capable of providing the measurement versatility needed to test a 3D IC as a whole and to also characterize its component parts, such as an FPGA or MEMS layer within a 3D IC package. A number of CAE software suppliers currently offer software design and simulation tools for 3D IC, including ANSYS (www.ansys, which also offers a free white paper on 3D modeling), Cadence Design Systems (, and Mentor Graphics (, and some IC suppliers, such as Xilinx, also offer software design support, but any software tools must carry considerable capabilities to effectively aid in the design of a practical 3D IC. For example, power planning for a 2D IC can be difficult, to provide adequate power for all components within a planar IC. But for a 3D IC, power planning becomes even more difficult, since so many die on multiple stacks of a packaged IC must be considered. Power distribution must be designed for the die, TSVs, and other portions of a multilayer 3D IC.

In addition, effective CAE software for 3D IC design should provide predictions not only of electrical performance at different operating temperatures, but of such parameters as thermal behavior and generation of electromagnetic interference (EMI). Thermal simulations alone can be challenging for a 3D IC with multiple layers and a possible mix of logic cells, digital and analog circuitry, power circuitry, and RF/microwave circuitry.

Designing for Test
Perhaps one of the most daunting challenges that remains for developers of 3D ICs is the creation of effective and affordable test solutions for these 3D ICs. Current test probe technology, for example, is geared for much larger linewidths and features than found in many proposed 3D ICs. In addition, modern probe stations with hundreds of probe tips may require modification to thousands of probe tips to provide sufficient numbers of contact points for testing 3D ICs. Effective testing of 3D ICs will most likely require that 3D ICs and their packages be designed for testing, with interconnections within the IC optimized for test probe access and even package pins designed for access to desired parts of a 3D IC.

Fortunately, major test-equipment manufacturers are well aware of the challenges facing developers of 3D ICs. Current test solutions are limited, often providing only access to external package pins. Enhanced solutions are needed to perform integrity checks on the inter-die connections within the package. Some test software developers, such as Synopsys (, have evaluated the needs of testing complex circuit designs, such as digital 3D ICs, and offer their DFTMAX test solution. It is a test tool that promises to reduce the costs of nanometer testing through dramatic reduction in test times even for multi-million-gate devices as well as significant reductions in test data.

In the end, the complexity of emerging packaged 3D IC devices will help to make life simpler for end users. With an electronics industry at work on fabs, design software, and test equipment to more cost-effectively produce complex 3D ICs, the end-user for the electronic products that these devices will serve, such as smart phones, tablet computers, and different types of sensors, will benefit with reliable products with greater functionality at lower costs.  

Interconnects for 3D packaging. (Photo: Advanced Packaging Center, Netherlands)

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