|Examining die for packaging. |
Growing demand for hand-held electronic devices has led to greater use of two-and-one-half-dimensional (2.5D) and three-dimensional (3D) packaging and in the handling of extremely thin wafers and dies. The material-supply industry has responded in providing newer generations of die attach films and wafer protection material to meet the needs of these increasingly demanding challenges. The advantages of using die-attach films at the wafer level instead of using die-attach materials on individual die have been known for some time, and it can be useful to explore the criteria for higher efficiency, more reliability, and higher performance die-attach film at the wafer level. This will include examining the effects of interconnections from chips to packages on choices of die-attach solutions. Packaging using wire-bonding, flip-chip soldering, or direct mechanical contact attach from flip-chip to bond pads effectively dictates the choice of different wafer level die-attach solutions.
|The illustrations show the steps of a typical manufacturing process with wafer-level packaging and how devices are integrated using dicing tape and die-attach films that are directly laminated on the wafer before dicing. |
In high-volume commercial applications, the use of 10-to-20µm die-attach film adhesive has proven to be reliable for stack-chip configurations from two to three layers. The 10-to-20µm film adhesive not only yields thinner devices well suited for computer tablets, cellular telephones, and digital cameras, but also uniform and controlled flow for very reproducible interconnections. Standard wire-bonding chip packaging employs backside die-attach that can use more traditional epoxy die-attached film adhesives than available from die-attach film adhesive manufacturers in the United States, such as AI Technology.
A typical manufacturing process employing wafer-level packaging is integrated in terms of using dicing tape and die-attach file direct laminated on a wafer before dicing. Such a process poses many material technology challenges, however, which have been met through the use of use of dicing-die-attach-film (DDAF) adhesives, from the US or Japan. The challenges include the following:
- Requirements for thin and stable film adhesives (typically epoxy based) that are only 10-to-25µm thick.
[N]DDAF adhesives that are compatible with the adhesive layer of the dicing tape to prevent cross-contamination leading to residues and other side-effects.
- Capability to perform chip-stack bonding with high efficiency.
- Capability for high die-bonding stability for wire-bonding operations to +250°C for high production rates.
- Use of DDAF materials that meet the performance requirements of at least JEDEC IPC level 3 or better for good moisture resistance after packaging. In terms of bonding stability and moisture sensitivity of the DDAF materials and the molding, encapsulation, or other electro-mechanical protection mechanisms, finished devices may range from level 3 to the best solutions meeting level 1 requirements. For high-temperature applications typically beyond +125 to +150°C, newer non-epoxy-based DDAF materials can withstand long-term use at +200°C and higher.
Traditional flip-chip packaging employs wire-bonding and solder-bump reflow for most requirements. Growing needs for higher speed, improved performance, and lower costs continue to drive semiconductor packaging towards shorter paths of interconnections between each level of a stacked-chip package.
Drive for Lower Costs
The drive for lower packaging costs has led to many innovative packaging solutions. The lowest-cost electronic devices, such as UHF radio-frequency-identification (RFID) tags, have been produced successfully in large volumes using direct flip-chip mechanical compression contact. (More on this on RFID manufacturing from Alien Technology is available from NIST at: http://usms.nist.gov/workshops/macroelectronics/05-Alien.pdf.). It should be noted that these low-cost RFID devices are limited to operating temperatures of less than +60°C and they do not provide stable operation in high-moisture environments.
|The three photos show semiconductor packaging from wafer DDAF to component on board. |
That contact resistance can be properly maintained for long-term use within specified temperature and environmental constraints provides hope that solutions for high-performance applications can be achieved with more engineered materials and packaging. For successful flip-chip packaging, the flip-chip underfill must also perform as a stable die bonding adhesive. For this to happen, a number of characteristics are required:
- The underfill adhesive must be easily placed either on the substrate or on the interconnection front side of the chip. DDAF will still be applicable. If paste underfill adhesive is to be useful, it must stay in place after being dispensed onto the substrate or chip.
- The underfill adhesive must not prevent contact when the chip and package substrate interconnections are lined and compressed for bonding. Unlike the use of Z-axis, uniaxial, conductive adhesive, any particulate matter could prove detrimental when forming interconnections.
- Flip-chip underfill adhesive should have a high glass transition temperature (Tg) and modulus to maintain good electrical contact and characteristics. For commercial and military applications, the Tg should be well above +150°C.
- The underfill adhesive should be as low in coefficient of thermal expansion (CTE) as the CTE of higher filled traditional epoxy underfills (<30 ppm/°C).
- For acceptable productivity, the underfill adhesive should cure at +175 to +250°C in less than 10 seconds.
- To meet the JEDEC/ IPC Level 1 moisture sensitivity requirements, the moisture absorption should be well below 0.5 percent in saturation.
There are now non-epoxy-based, high temperature, underfill-adhesives in paste or film format in thickness of 25 to 75µm for such applications.
TSV Stack Chip Packaging
Through-silicon-viahole (TSV) stack-chip packaging provides the ultimate chip interconnection performance for stack-chip packages. The requirement for stress relief is even more critical to filling in the viaholes of a TSV structure and between the stacked chips. For filling in TSV viaholes, fill-in adhesives must have certain features:
- Low viscosity to wick into the viaholes easily with the applied capillary force.
- Low CTE, preferably a great deal below 30 ppm/°C.
- High Tg and modulus to maintain good electrical contact and characteristics — for commercial and military applications, this should be well above +150°C.
- Fill-in adhesive should cure in less than 10 seconds at +175 to +250°C.
Non-epoxy-based , high-temperature fill-in paste adhesives are available that can fill in 20µm viaholes for such applications.
Wafer-level die-attach films with very thin bond lines pose many challenges. But recent advances in die-attach materials together with optimized processing techniques can overcome these challenges and will enable more advanced technology for packaging semiconductor devices within smaller footprints and volumes. Similarly, flip-chip underfill adhesive can provide effective fill-in of through-silicon viaholes and provide stress relief between stacked chips.
Contact: AI Technology, Inc., 70 Washington Road, Princeton Junction, NJ 08550-1012 800-735-5040 or 609-799-9388 fax: 609-799-9308 Web: http://www.aitechnology.com