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JTAG Boundary-Scan Testing Improves PCBs
Goepel's JULIET — JTAG Unlimited Tester.

Standards are an important part of maintaining quality in electronic products. Perhaps one of the most significant standards for manufacturing test applications at the printed-circuit-board (PCB) level is the JTAG or boundary-scan test standard established by the Joint Test Access Group (JTAG) consortium and introduced as an industry standard in 1990. The JTAG standard has proven to be an affordable and reliable test approach for PCB-level testing and is now used not only in manufacturing test applications, but for service and maintenance as well. Applications for JTAG technology range far and wide, from PCBs for low-cost consumer electronic products to the most elaborate of circuit boards for military and aerospace circuits and systems.

What is JTAG?
JTAG is defined by the Institute of Electrical and Electronic Engineers (IEEE, and the standard IEEE Standard-1149.1. More commonly known as boundary-scan testing, it was developed to assist in the testing and maintenance of assembled PCBs, especially as those circuits became increasingly dense. As a greater number of integrated circuits (ICs) began to replace discrete circuit components in the 1980s, and as more surface-mount-technology (SMT) components were used, PCBs grew in complexity and density and became more difficult to test. Traditional methods for testing those circuits with probers and test fixtures began to fall short, and the electronics industry sought better ways to test those circuits.

One of those ways is defined and described by the JTAG standard, which details how the testing of increased-density circuit elements such as ICs can be made easier by incorporating test circuitry within the circuit elements themselves. In fact, many ICs from leading suppliers now include JTAG circuitry to assist in the process of testing those ICs as well as the PCB on which they are mounted. The JTAG standard defines the interfaces, circuitry, and test features, including a boundary-scan register, and a minimal set of instructions for the testing of assembled PCBs. The JTAG standard also defines several types of language for programming, including one that allows a rigorous structural description of different functions, such as component-specific testability features, and another that describes how different testability features can be used.

Revisions to Standard
Revisions were made to the initial JTAG standard in 1993, to help clarify certain issues with the standard. In 1994, a supplement containing a description of the Boundary-Scan Description Language (BSDL) was added to the standard. The latest version of the IEEE standard is 1149.1-2013, which is supported by IEEE working group (WG) WG P1149.1 (also known by "Boundary Scan Architecture — Standard Test Access and Boundary Scan Architecture"). Copies of the full standard are available for purchase from the IEEE.

Why is a test approach such as JTAG even needed? In many cases, the shrinking dimensions of electronic circuitry and its components have spurred the development of such a test solution. In some cases, components are simply no longer accessible with probe tips. Today's push for increased circuit density in smaller electronic devices has resulted in many PCBs with components on both sides of the circuit board, and many of the circuit through-holes or circuit traces difficult if not impossible to access with a prober. Some components, such as SMT ball-grid-array (BGA) packaged components may have pins buried within the PCB or connections to the circuit board that are otherwise difficult to reach with a conventional prober. In addition, the compact size of today's PCBs doesn't always suggest obvious test points on the circuit board, making it again difficult to find a proper test point for a conventional prober.

Boundary-scan testing is capable of checking interconnections between components and ICs on a PCB without using physical test probes. It employs a boundary-scan cell to aid in the testing. This cell contains a multiplexer and latches to its pins, and it can capture data from pin or core logic signals. It can also drive data to different pins within the test circuitry. Serial connections to a PCB under test provide access to the captured data for analysis, and allow the sending of data to the device pins and circuitry of the PCB. The serial data path of a JTAG circuit is usually referred to as the scan path or scan chain. Boundary-scan testers offer direct access to nets to minimize the number of required test vectors as well as the required measurement time. Boundary-scan testers and measurements can potentially deliver much shorter test times and much lower equipment costs than traditional circuit testers.
JTAGTest is a hardware/software JTAG test solution from the Czech firm SeCons. .

Interconnection testing of JTAG compliant devices assumes that the devices are linked electrically by means of multiple nets, and that the integrity of these nets can be checked by analysis. The electrical connections between nets can be tested for short-circuit and open-circuit conditions, and a boundary-scan tester can check a component or circuit in comparison with expected results when attempting to detect faults between nets.

A JTAG test interface, which is often referred to as the test access port (TAP), employs a variety of different signals for testing, including test clock (TCK) signals for synchronization of devices, test mode select (TMS) signals for determining test states, test data in (TDI) signals, and test data out (TDO) signals. Signals travel along a serial scan path known as the boundary scan register (BSR).

Because JTAG boundary-scan testing capability makes practical sense for increasingly dense components and circuits, boundary-scan circuitry and JTAG logic is now almost routinely incorporated into highly integrated circuits, such as microprocessors and field-programmable gate arrays (FPGAs), helping to perform measurements on circuit boards with those components. Those seeking an excellent tutorial on boundary-scan testing can download the white paper from Corelis ( free of charge: "Boundary-Scan for PCB Interconnect Testing and In-System Programming of CPLDs and Flash Memories."

As JTAG technology has increased in popularity for interconnect testing on PCBs and for in-system programming (ISP) of ICs on those circuits, a growing number of firms are offering affordable JTAG test solutions for characterizing JTAG-compliant devices and circuits. Many of these test solutions include design-for-testability (DFT) rules to assist with JTAG testing and quick analysis of device interconnections without need for additional or advanced programming code.

Low-Cost Tester
For example, JTAGTest is a low-cost JTAG tester developed by SeCons (, an electronics firm from the Czech Republic. The JTAGTest tool is suitable for designers, production, and service applications, and can be used for debugging, prototyping, testing, and repairing PCBs. Although the software for this JTAG tester is somewhat dated (written for use on PCs with Microsoft 2000/XP/Vista operating systems), JTAGTest can use a PC to monitor internal signals or signals from device pins in real time without interfering with normal device operation, in compliance with the IEEE 1149.1 JTAG boundary-scan standard.

Another low-cost JTAG test solution, the JTAG Unlimited Tester (JULIET) from Goepel Electronic (, is a complete JTAG boundary-scan tester in a desktop system suitable for prototyping and production applications. It can be controlled by an external PC using a local area network (LAN) or Universal Serial Bus (USB) 2.0 connection, and can perform low-volume boundary-scan testing, ISP, and functional emulation testing with an exchangeable adaptor. Also, the JTAG ProVision software suite from JTAG Technologies ( runs on a PC and provides a straightforward means of creating boundary-scan tests and ISP applications for different PCBs

JTAG testing offers an efficient and effective means of checking PCBs and their components for interconnection quality and integrity. It is a practical test approach that can be implemented in low-cost solutions, and that is capable of performing high-speed testing of production-line PCBs that can contribute to less time and expense on producing reliable PCB products at reduced cost.  

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