Monday, September 25, 2017
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New eBook from ASSET explains faster parallel programming of memories via JTAG on manufacturing lines
RICHARDSON, TX – Programming memory on the manufacturing line after the devices have been soldered to a circuit board must be accomplished quickly to keep pace with the assembly process. Unfortunately, the capacity of flash has gotten so large and the amount of data being programmed into them so extensive that the process has slowed considerably.

A new eBook published by ASSET® InterTech (www.asset-intertech.com) explains how distributed architectures and on-board field programmable gate arrays (FPGA) accessed via JTAG can be deployed to accelerate in-line in-system programming (ISP) without jeopardizing the manufacturing beat rate.
“Parallel programming – or loading data into multiple circuit boards simultaneously – speeds up the process by orders of magnitude,” said Kent Zetterberg, technical product manager for the ScanWorks® platform for embedded instruments. “In addition, a programming engine can be temporarily inserted into an on-board FPGA to program multiple devices on the same board at the same time. When you start adding up all of the factors, you’ve got a really fast in-line programming process.”

Titled “Fast Flash Parallel In-System Programming”, the new eBook is available for free and can be downloaded from the eResources center on the ASSET website at http://www.asset-intertech.com/Products/Boundary-Scan-Test/BST-Software/Fast-Flash-Parallel-In-System-Programming-ISP-JTAG

Other informative eBooks, white papers and videos on issues relating to chip, board and system debug, validation and test can be downloaded from the ASSET website at: http://www.asset-intertech.com/eResources
 

ASSET and ScanWorks are registered trademarks and Arium and SourcePoint are trademarks of ASSET InterTech, Inc.

ASSET and ScanWorks are registered trademarks and Arium and SourcePoint are trademarks of ASSET InterTech, Inc.

 
 
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