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Boundary Scan Integration on Flying Probe Testers
SPEA 4050 flying probe tester.

In the 1980s, the electronics test industry faced challenges related to more complex, densely populated printed-circuit boards (PCBs) and more difficult access to test points. The increasingly smaller sizes of electronic devices drove the design of denser and more complex PCBs. The design constraints in some cases, such as wireless-capable boards, dictated that minimal if any test pads would be placed on some circuit boards. Traditional in-circuit-test (ICT) bed-of-nails testers could not provide adequate test coverage for these more complex circuit boards mainly due to the loss of access to components and nets on the circuit boards. In response to these challenges of limited access for testing on PCBs, flying probe testers and boundary-scan testers were both introduced.

Flying Probe Technique
Flying probe testers access PCB nodes through multiple flying nails. Unlike bed of nails test systems, flying probe testers do not require test pads to make contact with nodes on a circuit board. In addition, a flying probe tester does not require a fixture, which results in a substantial cost savings advantage over bed-of-nails testers. Since the fixture build was not required with flying probe programs, the time required for the test program to be ready for production also decreased dramatically.
The boundary-scan test concept (per JTAG Technologies B.V., 2008).

Typical tests performed on a flying probe system include analog components tests, shorts testing, open pin testing, and optical measurements. Additional bias power may also be added as part of the testing. Since a flying probe tester relies on movement of the heads for positioning before making probe contact, the overall test time is slower compared to a traditional ICT bed of nails tester.

Boundary Scan Technique
Boundary-scan testing became the IEEE 1149.1 standard in 1990. The testing concept involves accessing the nodes of a circuit through boundary-scan cells that are built into the integrated circuits (ICs) on a PCB under test. To comply with the test standard, a device must include a four-wire (five-wire if optional reset signal is included) test access port (TAP), internal boundary-scan cells for each pin, associated internal boundary-scan registers, and additional multiplexing circuitry. In addition, the device vendor must provide Boundary Scan Description Language (BSDL) files that fully describe the boundary-scan implementation in the associated devices (JTAG Technologies B.V., 2008).
Increase of coverage possible with flying probe and boundary-scan integration.

Typical tests executed during a boundary-scan test are interconnect test and infrastructure test. Cluster testing, memory testing, and flash programming are also available. The infrastructure test is meant to find major connectivity problems during a boundary-scan test. The interconnect test verifies the integrity of all boundary-scan testable nodes on the circuit board.

A flying probe tester is capable of testing the majority of the board using almost any contact point that is not covered. Examples of the points that a flying probe cannot access include back-to-back BGA pins, package on-package (PoP) pins, etc. On the other hand, a boundary-scan tester will be able to access some of the pins inaccessible to a flying probe tester, provided that there are boundary-scan cells available for those pins.

A flying probe tester uses physical movement of the probes to make contact with the circuit board. The physical movement of the probes during test contributes to the majority of test time. To perform tests for shorts on IC pins, flying probes must be placed on the pins first. Once shorts tests for a current group of pins have been performed, the probes must be moved to other pins to test for shorts.

Boundary-scan testing does not rely on any physical movements, so shorts tests can be performed much faster than shorts tests performed using the flying probe approach.

Generally speaking, boundary-scan testers are equipped to detect lifted pins on ICs if a boundary-scan cell can sense a logic level coming from an external source. This external source in this case may be another boundary scan cell from another IC interconnected through a PCB trace. Other possibilities include pull up, pull down circuit configurations, and also other non-boundary-scan devices that are capable of supplying a logic level to the boundary-scan cell.
Another view of integrating boundary-scan and flying probe testers.

There are some general guidelines that a design engineer should use to increase testability on a PCB but, generally speaking, a lack of Design for Test (DFT) on a circuit board is not a problem for a flying probe test. In contrast, boundary-scan testers depend heavily on DFT implemented on the circuit board and ICs to be tested. A design engineer needs to implement boundary-scan conditions on a circuit board by providing TAP connections and proper connections for ICs, whereas a product engineer may need to ensure that the boundary-scan-compatible version of an IC is available and the connector for the TAP can be mounted.

For measurements performed with a flying probe tester, a benefit can be to speed up a test. When test speed is important, a flying probe test program may be optimized to take advantage of the shorts and open pins tests that are already performed by a boundary-scan tester.

Added Access
For measurements performed with a boundary-scan tester, a benefit may be in terms of added access and therefore increased nets and pins coverage. Flying probes in this case can be programmed to function as virtual boundary-scan cells to provide input signals to boundary-scan cells and to measure the output signals from the boundary-scan cells.

In a typical test setup, boundary-scan hardware will control all of the digital vectors involved in the boundary-scan test. The digital boundary-scan vectors include both the TAP port and the digital signals through flying probes. The TAP port signals are generated directly by the boundary-scan controller, whereas the digital signals on flying probes are generated and sensed by the flying probe tester.

Flying probe hardware must be in control of the probe movements. This is done for safety reasons and also to avoid any probe collisions. If the boundary-scan controller must either drive or sense a signal on a net on a circuit board under test, the boundary-scan software will specify which net it needs and the flying probe will move and position an appropriate probe in that location.

Software integration typically requires specially written dynamic-link-library (DLL) files for the boundary-scan controller to communicate with the flying probe tester. The DLL files facilitate several aspects of integration including proper test flow, sharing of information to optimize the tests, test result reporting, and combined test coverage reporting.

Case Studies
Several case studies have been performed on the integration of the two test approaches. These studies reveal that one technology may benefit more from the integration than the other, and also that the combined test time is not always faster than when performing the two tests separately. Either way, the studies reveal, the combined final test coverage is greater compared to each of the technologies used separately.

In the first case study, the circuit board under test had 331 nets and 335 components. The overall combined test time in this case increased by 16 percent.

In the second case study, the number of total nets on the board was 8915 and the total number of components was 5530. The overall combined test time in this case decreased by 37 percent.

The flying probe and boundary-scan test techniques have both been developed to target the problem of net access in order to test circuit boards. Comparison of the two techniques reveals weaknesses in both approaches. Both techniques may run into net access issues. The speed of testing with a flying probe tester is generally much slower than a boundary-scan tester when compared side by side for the same tests. Even though the ICs may be boundary scan compatible, a lack of DFT on the board may dramatically decrease the net coverage when using a boundary-scan tester. Case studies reveal that combining the two techniques improves the overall test coverage on a circuit board.

While the test coverage increases when combining the two techniques, the overall test time may either decrease or increase. There are several factors that may influence the overall test time, including the complexity of the circuit board, the design for testability, etc. There may not be an easy way to tell ahead of time if combining the two test techniques will result in both an increase in coverage and a decrease in test time. Instead, an analysis will have to be performed for each circuit board to fully assess the outcome.


Contact: SPEA America, 2609 SSW Loop 323, Tyler, TX 75701 903-595-4433 fax: 903-595-5003 E-mail: Web:

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