Tuesday, May 24, 2016
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New tutorial discusses diagnosing defects and variances on DDR memory buses and high-speed serial IO
RICHARDSON, TX  – Slight variances and defects on circuit boards are more difficult than ever to detect and diagnose. Plus, they can result in system crashes and degrade performance later on because their harmful effects are cumulative. A new tutorial by ASSET InterTech (www.asset-intertech.com) investigates how advanced test and debug tools based on instruments embedded in chips are able to identify the root causes of defects and variances in complex chips and circuit boards.

“What we’ve seen is that in an era of shrinking chip and board geometries, higher speeds, and greater densities, legacy test technologies no longer provide the access and defect coverage they once did,” said Adam Ley, Chief Technologist, Non-intrusive Board Test and JTAG, for ASSET InterTech and one of the three authors of the tutorial. “Even the slightest operational variance outside of the board’s specified tolerances could cause problems later when performance degrades or intermittent system crashes occur.”

A Tutorial: Detection and Diagnosis of Printed Circuit Board Defects and Variances” is available now on the ASSET website at http://asset-intertech.com/Products/Boundary-Scan-Test/BST-Software/Tutorial-Board-Test-DDR3-DDR4-Memory-Serial-IO .
Other informative eBooks, white papers and videos on issues relating to chip, board and system debug, validation and test can be downloaded from: http://www.asset-intertech.com/eResources

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