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JTAG/Boundary Scan Makes Dependable Test Connections
For effective application of JTAG/boundary scan testing, test points are included as part of the design of a new component.

Shrinking, densely populated printed-circuit boards (PCBs) and electronic assemblies make efficient electronic testing of electronic products ever more challenging. Compact assemblies and components create serious issues in terms of mechanical test-point access when it is time to develop test strategies for these circuits. And today's BGA packaging and high-speed transmission lines require high-performance test solutions. Fortunately, JTAG/boundary scan test methods provide effective, practical solutions for measurements on extremely compact, densely packed circuits, for the engineering and development departments of both small and large electronic companies.

In 1990, the Joint Test Action Group (JTAG) developed an IEEE specification for boundary scan testing known as IEEE Standard 1149.1-1990, with a supplement added in 1994 to describe the boundary scan description language (BSDL) used to define devices under test. Devices and circuits that incorporate JTAG/boundary scan test capabilities include shift-register cells which can be connected in a dedicated path around the circuit's boundary. This signal path enables control and testing of a circuit or device for effective characterization. Testing by means of a boundary scan is usually defined by a circuit's designer in a BSDL file, with digital signals used in the testing defined in a boundary scan register (BSR). Commercial JTAG test systems can work with the BSDL models developed for different JTAG-compliant circuits and devices to create usable test applications, such as for evaluating the integrity of interconnections and the performance of memory circuits. Additional models can serve in the testing of non-BSDL model components, such as RAM or driver ICs.

Evaluating Components and Circuits
A JTAG/boundary test system provides the models and required computer-aided-design (CAD) data (as a net list) for evaluating components and circuits during their prototype stages. Tests can be generated for the first prototypes, which can be tested with the same quality and test depth as final serial products. With this test approach, the test bus required is available on the early unit under test (UUT) and can be used to load field-programmable-gate-array (FPGA) or complex-programmable-logic-device (CPLD) components or to put the boot loader into the program flash.
Circuits designed for JTAG/boundary scan testing include access points for test signals and signal analysis.

Although the JTAG/boundary scan approach involves circuit designers, rather than test engineers, creating tests for their circuits, it could be argued that they know their product as well as anyone and are well qualified to create those tests. Having them involved can also reduce the time, complexity, and cost of developing a test solution for the circuits. The JTAG/boundary scan approach also makes it possible to test the first prototype with the same methods as used for the serial product, with the same test depth and the same pin-level fault information for efficient testing. In addition, the test archive data is available to be passed along to EMS personnel. A contract manufacturer does not have to coordinate test generation for a given electronic product.

Information between a JTAG test system and a boundary scan component is transferred by means of a four-wire test bus. When developing a product that will be tested by means of JTAG/boundary scan methods, the test bus must be considered as part of the product design, for example, replacing the test points that would have been determined for an in-circuit test (ICT) or flying probe test (FPT) measurement approach. Because test points are not required with the JTAG/boundary scan approach, there aren't the same access problems as for ICT or FPT. In typical circuit or component for JTAG/boundary scan testing, boundary scan cells are located between a component's pins and its inner logic, so that the core logic no longer plays a role for testing board circuitry. It doesn't matter if the device being testing is a microprocessor or a programmable logic device (PLD).

During testing with a JTAG/boundary scan system, a boundary scan component is switched to external test mode (EXTEST). This is done by means of a signal interchange at the component's Test Clock (TCK) and Test Mode Select (TMS) as well as setting a respective command via Test Data Input (TDI). At this point, the inner logic of the device under test is separated from the pins. Now, the boundary scan cell is exclusively responsible for the signal level at the component pin. Loaded with a digital 1 or 0, a high level or low level is driven, respectively. Generally, there is a boundary scan cell at each pin for level measurement. This helps to verify the test pattern and therefore check interconnections.

Following Design Rules
As with any test technology, JTAG/boundary-scan testing employs design rules that must be followed. If these design rules are disregarded, measurement accuracy and effectiveness can be degraded, or measurement capability completely lost. Because of such design rules, it is possible to have a board that cannot be tested because of one missing, required interconnection. Fortunately, convenient and available software helps simplify the task of complying with rule requirements for JTAG/boundary-scan testing. Such design rules also reinforce the fact that it makes sense to start with test generation and measurement planning at a very early stage of a product's design and development. Once a layout is finalized, it is difficult to make any changes necessary to accommodate, for example, JTAG/boundary-scan test requirements.

JTAG/boundary-scan testing is an efficient means for characterizing digital circuits, especially when it is implemented at the design stage. It provides numerous advantages and insights into a circuit's performance, making possible completely new measurements of performance quality. JTAG/boundary-scan methods enable high-value testing as early as the first prototype stage; in-system programming and testing using the same interface; and an ideal interface for electronic-manufacturing-services (EMS) requirements. With growing trends towards smaller packages and higher-density electronic circuits with limited mechanical pin access, JTAG/boundary scan methods offer proven and dependable solutions for testing those circuits.

Contact: Goepel electronic LLC, 9737 Great Hills Trail, Suite 170, Austin, TX 78759 888-446-3735 or 512-782-2500 fax: 734-471-1444 E-mail: Web: or

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