|Typical packages for high-power semiconductors. |
Recently, IHS Research (www.ihs.com) announced a forecast for power semiconductors with an expected compound annual growth rate of 8 percent. This figure is slightly less than in previous reports, but still indicates the potential of this market. The demand for power semiconductors is mainly driven by environmental trends such as attempts to save energy and investment in clean energy. The efforts for more sustainability and more efficient use of electricity can be predominantly found not only in the industrial and the automotive segments but also in the consumer electronics industry.
Some typical applications are solar and wind power generation plants in the industrial field, and the electric power steering and idling-stop systems in cars as used in hybrid electric vehicles. In the consumer electronics market, so-called white goods striving for energy savings will be a major application. Air conditioners, refrigerators, and washing machines are examples in this segment. Besides a higher general environmental awareness and a general understanding of the limitation of resources, governmental subsidy policies in many countries further support this.
|Multitest MT2168 has proven capable of handling high-power semiconductor testing. |
Many of the established semiconductor manufacturers offer power ICs and power discrete devices. The package types are often very mature. They represent well-established processes but, at the same time, they are not optimized for today's state-of-the-art production methods. Packages such as TO, SO, and QFN are used. For extreme current requirements, IGBT Power Modules are applied. Also, dedicated and more exotic packages are often used for power applications.
Final DUT Testing
Is the final test of these devices the same from process to process? Final test is a functional test of the device before the semiconductors are shipped to customers. Many people, who are not directly involved in the back-end processes of semiconductor manufacturing, are not aware of this very last step in production. Those who are aware of final test do not like it: It adds cost, but no value, except to ensure the quality of the part.
|Lemsys Tester, model TRds 2015-2020. |
Reliable functionality of power semiconductors is a key for critical applications such as in motor vehicles. For other applications, it is simply more cost-efficient to work with a tested package rather than taking the risk that a malfunction will be discovered only after the semiconductor is already mounted in the final product.
The typical test set for this final test includes an automatic-test-equipment (ATE) tester, a handler, a load board, and one or more contactors. The tester performs measurements, evaluates the test results and is capable of diagnosing faults. The handler loads the devices from their transport media (e.g. a JEDEC tray or a tube), soaks them to the required test temperature, then inserts them into the contactor and finally sorts them according to the test results. Load board and contactor(s) are electrical interfaces between the device under test (DUT) and the tester. Whereas the load board is designed according to the tester requirements, the contactor is the socket where the DUT is inserted for test and therefore is more precisely determined by the package itself.
General requirements for final test also apply to final test for power semiconductors. There are some general conditions that must be fulfilled by the test cell and its components to be as cost-efficient and productive as possible, and they are valid for power semiconductors accordingly.
Measurement accuracy is essential to provide meaningful information about the device under test, in production as well as in development; for the handlers, it is positioning accuracy to ensure highest yield and thermal accuracy for test at hot (up to +200°C) or cold (down to -55°C) temperatures, e.g. for automotive applications. The maximum temperature drift for high power automotive applications is in the range of ±3°C at the test site.
For the tester, measurement speed is the actual time needed to perform the electrical test (the test time). For a handler, it is the time needed for internal material transportation, time for soaking, and time for exchanging the DUT at the contact site to the tester. State-of-the art testers feature short test times. The handler must be fast enough to not limit the tester's capabilities. Maximum achievable overall speed directly transfers to test cell throughput. With low throughput, the test cell can create a potential bottle neck of the entire production process.
Reliability of the test cell equipment avoids unscheduled downtime. It also ensures the reliability of the test results that may be otherwise negatively influenced by bad contacting performance, mis-sorting of the packages after test, etc. Modularity helps the test equipment to evolve and adapt to changing needs. This can be achieved primarily through the modularity of the entire test cell as well as the tester and handler on their own.
Special requirements in testing high-power semiconductors add more challenges.
Performing tests at high-power levels is a challenge in itself. Special requirements concern not only the tester (ATE), but also the test interfaces (load board and contactor). Safety issues because of the high-voltage/high-current situations must be considered. Arcing is another concern. Steps must be taken to avoid damage of the test equipment from arcing. Finally, thermal stability during testing must be ensured.
Testers should exhibit low parasitic effects, so as to have a minor part in the test results: This point is very important in power semiconductors testing. Modularity and removable devices-under-test inevitably lead to increased connection wires and therefore to increased parasitic inductances when compared with operation in industrial power converters. This parasitic effect must be reduced as much as possible in order to not reduce the testing capability of the ATE (achievable di/dt and safe testing area). This requirement becomes more and more important when the current-over-voltage rating of a DUT increases.
Dedicated handler setups can ensure the required temperature accuracy at the DUT by advanced thermal-control features. These setups can also take care of the measurement and adjustments needed at the DUT while it is inserted. Doing this at the soak station only is not sufficient.
To avoid arcing, clamping of the DUT should be performed with dedicated materials and design. Also, high-voltage/high-current test levels are potentially life-threatening to operators. A handler must have safety features that stop testing as soon as the handler is no longer docked to the tester. This mechanical requirement must be recognized by the handler and communicated to the tester.
Large packages are often deployed for power semiconductors. This requires sufficient soak capacity of the handlers. Otherwise soaking will slow down the handler and finally, decrease the test cell throughput. Most high-power semiconductors are tested single site (one DUT inserted at one point in time). However, once parallelism increases, the handler must support the load board design with sufficient widely spread contact sites.
|Image showing the thermal stress of the contactor. pin during test at 200 A. |
A combination of higher currents, lower voltages, and faster switching speeds are creating increased problems with power distribution network (PDN) design and thermal control on the device interface board (DIB). Those designers who take a "rule of thumb" approach to PDN design are now getting caught by inadequate or inappropriate decoupling strategies and networks whereby the entire loop inductance budget is used on the board.
Power Supply Parameters
Power supply planes, choice of capacitor, and capacitor placement, as well as the return path of the power supply, must all be carefully considered in order to prevent IR drop problems. Power supply sensing must be considered on an application specific basis instead of a "one size fits all" approach for the test system.
Just as increasing signal speeds led to an increase in high-speed simulation, the new demands on PDN design is now leading to a focus on "Power Integrity" simulation, and, while this is currently much less well understood than traditional signal integrity, the time is approaching when it will become essential in order to achieve a successful result.
The DIB designer must ensure that heat generated within the board due to high current (particularly under large BGAs) does not approach the glass transition temperature (Tg) of the board material. However, in the specific area of ATE where thermal stability is critical, it is also important not to create such an effective heat sink that the board influences the stability of "hot" testing.
There are two major issues that contactors for high-power semiconductors need to address: resistance stability and temperature stability. Thermal management and highly accurate symmetry to share the current load is crucial for high-current applications, as some applications run up to several hundred amperes and current is shared by more than one contact pin. In addition, heat that will be caused by high currents must be reliably dissipated by the right materials using innovative designs. Only contactors optimized for these challenging applications will have a reasonable life span.
Resistance stability is influenced by the contact spring itself AND the condition of the device pin. Since TO/DIP packages are often used for these high-power applications, old molding tools are utilized, which generate an extreme amount of debris/mold flashes on the IC leads. This nonconductive debris causes high contact failure rates.
Temperature stability is not easy to achieve in a high-power device test system. Due to the inductance requirement for fast signals, the length of the contactor pin is limited. A short length limits the space of thermal insulation in the contact area. In addition, the contact springs will be quite sizeable to carry the current, which will result in good thermal coupling between board and IC. Many massive copper layers in the board will also act like a "big heat sink." Integrated solutions of load board and contactors with insulation on the test-side of the load board are one approach to ensure the required temperature accuracy.
|Multitest ecoAmp Kelvin contactor dedicated to high power testing. |
In conclusion, performing final test on high-power semiconductor devices is an electrical challenge, but also requires partnership solutions of the equipment suppliers. Generally, the testing of power semiconductors follows the rules of standard semiconductor test, but adds even more comprehensive requirements to the test cell components. As power semiconductors are seen as a prospective market, special solutions have emerged and will further be developed. Some examples are the Lemsys tester (TRds 2015-2020), and the Multitest ecoAmp Kelvin contactor. To address the special test requirements of power semiconductors, optimizing each single test cell component individually, will not result in a satisfying performance. Optimum test setups can be developed by interdisciplinary collaboration of the suppliers of the tester, handler, load board, and the contactor.
Understanding the features of the other test cell components, which are particular to the support of high power test, is a start. Defining ideal interfaces supporting these features can be the next step. At the end of the day, equipment vendors need to comprehend the overall set-up and finally deploy methods of value engineering across all components to optimize the functions and features. The handler-tester communication to avoid safety issues and the thermal insulation on the load board are some examples of this approach, which have already been worked out.
Contact: Multitest Electronic Systems, Inc., 4444 Centerville Road, Suite 105, St. Paul, MN 55127-3700 651-407-7777 fax: 651-407-7290 E-mail: email@example.com Web: http://www.multitest.com