Richardson, TX — ASSET® InterTech's ScanWorks® IJTAG Test tool has been given improvements for its graphical viewer and now has significantly faster performance. These enhancements allow engineers to access, control and automate the operations of test and measurement instruments embedded in chips.
|ScanWorks IJTAG Test's instrument map (iMAP). |
ScanWorks IJTAG Test was the first suite of tools supporting the new IEEE P1687 Internal JTAG (IJTAG) standard for embedded instrumentation. IJTAG gives chip designers a more effective method for debugging chip designs by standardizing the way engineers control and access the instruments they have embedded on-chip. In addition, these same embedded instruments can be re-applied later to test, validate and debug prototypes of circuit board designs and manufactured boards.
Users of ScanWorks IJTAG Test have deployed the tool in a variety of applications. Some are validating IJTAG structures that have been integrated into SoCs and application-specific integrated circuits (ASIC). Others have implemented the tool in prototype circuit board bring-up and in board manufacturing itself. One user is employing ScanWorks IJTAG Test to access embedded instruments by way of IJTAG and other on-chip structures, such as those specified in the IEEE 1500 standard for embedded core test.
ScanWorks IJTAG Test tools can read IJTAG's two languages — Instrument Connectivity Language (ICL) and Procedural Description Language (PDL). ICL defines the access connections for the instruments embedded on-chip while PDL is an extension of the popular Tcl (Tool Command Language) for programming validation, test and debug vectors to be executed by embedded IJTAG instruments. With the graphical user interface on ScanWorks IJTAG test engineers can drag-and-drop instruments and specific operations to automatically develop test routines.
The IJTAG standard recently passed a significant milestone on the road to approval. In advance of its going to ballot, the draft of the specification has been submitted to the IEEE's Mandatory Editorial Coordination (MEC) process, which determines whether the draft of the specification conforms to the IEEE's editorial requirements. Following the MEC review, IEEE balloting to ratify the IJTAG standard can begin.
Contact: Asset InterTech, 2201 N. Central Expy., Ste. 105, Richardson, TX 75080 888-694-6250 or 972-437-2800 fax: 972-437-2826 Web: http://www.asset-intertech.com